[논문]A Design of a Wireless Power Receiving Unit With a High-Efficiency 6.78-MHz Active Rectifier Using Shared DLLs for Magnetic-Resonant A4 WP Applications

Hyung-Gu Park; Jae-Hyeong Jang; Hong-Jin Kim; Young-Jun Park; SeongJin Oh; YoungGun Pu; Keum Cheol Hwang; Youngoo Yang; Kang-Yoon Lee

doi:10.1109/TPEL.2015.2468596

A Design of a Wireless Power Receiving Unit With a High-Efficiency 6.78-MHz Active Rectifier Using Shared DLLs for Magnetic-Resonant A4 WP Applications

IEEE transactions on power electronics, v.31 no.6, 2016년, pp.4484 - 4498

Hyung-Gu Park (Coll. of Inf. & Commun. Eng., Sungkyunkwan Univ., Suwon, South Korea) , Jae-Hyeong Jang (Coll. of Inf. & Commun. Eng., Sungkyunkwan Univ., Suwon, South Korea) , Hong-Jin Kim (Coll. of Inf. & Commun. Eng., Sungkyunkwan Univ., Suwon, South Korea) , Young-Jun Park (Coll. of Inf. & Commun. Eng., Sungkyunkwan Univ., Suwon, South Korea) , SeongJin Oh (Coll. of Inf. & Commun. Eng., Sungkyunkwan Univ., Suwon, South Korea) , YoungGun Pu (Coll. of Inf. & Commun. Eng., Sungkyunkwan Univ., Suwon, South Korea) , Keum Cheol Hwang (Coll. of Inf. & Commun. Eng., Sungkyunkwan Univ., Suwon, South Korea) , Youngoo Yang (Coll. of Inf. & Commun. Eng., Sungkyunkwan Univ., Suwon, South Korea) , Kang-Yoon Lee (Coll. of Inf. & Commun. Eng., Sungkyunkwan Univ., Suwon, South Korea)

Abstract ▼ AI-Helper

This paper presents a full-CMOS wireless power receiving unit (WPRU) with a high-efficiency 6.78-MHz active rectifier and a dc-dc converter for magnetic-resonant alliance for wireless power (A4WP) applications. The proposed high-efficiency active rectifier with delay-locked loop (DLL) is a highly efficient receiver circuit intended for use in resonant wireless charging applications with a resonant frequency of 6.78 MHz. Each MOSFET of the proposed rectifier is turned on and off based on the ac input voltage. The delay between the ac input current and the ac input voltage due to the delays of internal blocks such as voltage limiter, level shifter, gate driver, and comparator will cause the reverse leakage current, degrading the power efficiency. Thus, the proposed active rectifier adopts the DLL to compensate for the delay caused by internal blocks, which leads to the removal of reverse leakage current and the power efficiency maximization. Moreover, to maximize power efficiency, negative impedance circuit (NIC) is also adopted to minimize switching loss. In the case of dc-dc converter, phase-locked loop is adopted for the constant switching frequency in process, voltage, and temperature (PVT) variation to solve the efficiency reduction problem, especially by heat. This chip is implemented using 0.18 mu m BCD technology with an active area of 3.5 mm x 3.5 mm. When the magnitude of the ac input voltage is 8.95 V, the maximum efficiencies of the proposed active rectifier and dc-dc converter are 91.5% and 92.7%, respectively. The range of ac input voltage is 3-20 V, and the efficiency of the WPRU is about 80.86%.

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A Design of a Wireless Power Receiving Unit With a High-Efficiency 6.78-MHz Active Rectifier Using Shared DLLs for Magnetic-Resonant A4 WP Applications

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A Design of a Wireless Power Receiving Unit With a High-Efficiency 6.78-MHz Active Rectifier Using Shared DLLs for Magnetic-Resonant A4 WP Applications

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