참고문헌 (18)

1. Liu, L., Arreghini, A., Van den bosch, G., Pan, L., Van Houdt, J.. Comprehensive understanding of charge lateral migration in 3D SONOS memories. Solid-state electronics, vol.116, 95-99.

   상세보기

2. 10.1109/IRPS.2011.5784550 

   

3. Sentaurus Device User Guide version E-2010 12 2010 

4. Padovani, A., Arreghini, A., Vandelli, L., Larcher, L., Van den bosch, G., Pavan, P., Van Houdt, J.. A Comprehensive Understanding of the Erase of TANOS Memories Through Charge Separation Experiments and Simulations. IEEE transactions on electron devices, vol.58, no.9, 3147-3155.

   상세보기

5. 10.1109/IEDM.2015.7409636 

   

6. 10.1109/IEDM.2007.4418970 

   

7. Chou, S.Y., Antoniadis, D.A.. Relationship between measured and intrinsic transconductances of FET's. IEEE transactions on electron devices, vol.34, no.2, 448-450.

   상세보기

8. Proc IEEE Non-Volatile Semiconductor Memory Workshop The air spacer technology for improving the cell distribution in 1 giga bit NAND flash memory kang 2006 10.1109/.2006.1629483 36 

   

9. IEDM Tech Dig A highly manufacturable low-k ALD-SiBN process for 60nm NAND flash devices and beyond kim 2004 1063 

10. IEDM Tech Dig Novel 3-dimensional dual control-gate with surrounding floating-gate (DC-SF) NAND flash cell for 1Tb file storage application whang 2010 668 

11. 10.1109/VLSIT.2012.6242458 

    

12. Park, Young-Bog, Schroder, D.K.. Degradation of thin tunnel gate oxide under constant Fowler-Nordheim current stress for a flash EEPROM. IEEE transactions on electron devices, vol.45, no.6, 1361-1368.

    상세보기

13. Maconi, A., Compagnoni, C. M., Spinelli, A. S., Lacaita, A. L.. New Erase Constraint for the Junction-Less Charge-Trap Memory Array in Cylindrical Geometry. IEEE transactions on electron devices, vol.60, no.7, 2203-2208.

    상세보기

14. Maconi, A., Arreghini, A., Monzio Compagnoni, C., Van den bosch, G., Spinelli, A.S., Van Houdt, J., Lacaita, A.L.. Comprehensive investigation of the impact of lateral charge migration on retention performance of planar and 3D SONOS devices. Solid-state electronics, vol.74, 64-70.

    상세보기

15. Lee, K.H., Degraeve, R., Toledano-Luque, M., Arreghini, A., Breuil, L., Blomme, P., Van den bosch, G., Van Houdt, J.. Assessment of tunnel oxide and poly-Si channel traps in 3D SONOS memory before and after P/E cycling. Microelectronic engineering, vol.147, 45-50.

    상세보기

16. VLSI Symp Tech Dig Vertical cell array using TCAT(terabit cell array transistor) technology for ultra high density NAND flash memory jang 2009 192 

17. VLSI Symp Tech Dig Pipe-shaped BiCS flash memory with 16 stacked layers and multi-level-cell operation for ultra high density storage devices katsumata 2009 136 

18. 10.1109/RELPHY.2007.369887