참고문헌 (18)

1. Wong, Koon-Lun Jackie, Rylyakov, Alexander, Yang, Chih-Kong Ken. A 5-mW 6-Gb/s Quarter-Rate Sampling Receiver With a 2-Tap DFE Using Soft Decisions. IEEE journal of solid-state circuits, vol.42, no.4, 881-888.

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2. IEEE ISSCC Dig Tech Papers A time-based receiver with 2-tap DFE for a 12 Gb/s/pin single-ended transceiver of mobile DRAM interface in 0.8 V 65 nm CMOS yi 2017 400 

3. Proc IEEE Symp VLSI Circuits A low-EMI four-bit four-wire single-ended DRAM interface by using a three-level balanced coding scheme yi 2016 1 

4. Bucher, Michael, Kollipara, Ravi T., Su, Bruce, Gopalakrishnan, Liji, Prabhu, Kashinath, Venkatesan, Pravin Kumar, Kaviani, Kambiz, Daly, Barry, Stonecypher, B. William F., Dettloff, Wayne, Stone, Teva, Heaton, Fred, Yi Lu, Madden, Chris, Bangalore, Sanath, Eble, John C., Nguyen, Nhat M., Lei Luo. A 6.4-Gb/s Near-Ground Single-Ended Transceiver for Dual-Rank DIMM Memory Interface Systems. IEEE journal of solid-state circuits, vol.49, no.1, 127-139.

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5. Byungsub Kim, Yong Liu, Dickson, T.O., Bulzacchelli, J.F., Friedman, D.J.. A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS. IEEE journal of solid-state circuits, vol.44, no.12, 3526-3538.

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6. Dickson, T.O., Bulzacchelli, J.F., Friedman, D.J.. A 12-Gb/s 11-mW Half-Rate Sampled 5-Tap Decision Feedback Equalizer With Current-Integrating Summers in 45-nm SOI CMOS Technology. IEEE journal of solid-state circuits, vol.44, no.4, 1298-1305.

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7. Nazari, Meisam Honarvar, Emami-Neyestanak, Azita. A 15-Gb/s 0.5-mW/Gbps Two-Tap DFE Receiver With Far-End Crosstalk Cancellation. IEEE journal of solid-state circuits, vol.47, no.10, 2420-2432.

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8. IEEE ISSCC Dig Tech Papers A 0.25 pJ/b 0.7 V 16 Gb/s 3-tap decision-feedback equalizer in 65 nm CMOS bai 2014 46 

9. Shahramian, Shayan, Carusone, Anthony Chan. A 0.41 pJ/Bit 10 Gb/s Hybrid 2 IIR and 1 Discrete-Time DFE Tap in 28 nm-LP CMOS. IEEE journal of solid-state circuits, vol.50, no.7, 1722-1735.

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10. IEEE ISSCC Dig Tech Papers A 0.45-to-0.7 V 1-to-6 Gb/s 0.29-to-0.58 pJ/b source-synchronous transceiver using automatic phase calibration in 65 nm CMOS choi 2015 66 

11. Kim, J., Horowitz, M.A.. Adaptive supply serial links with sub-1-V operation and per-pin clock recovery. IEEE journal of solid-state circuits, vol.37, no.11, 1403-1413.

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12. Balamurugan, Ganesh, Kennedy, Joseph, Banerjee, Gaurab, Jaussi, James E., Mansuri, Mozhgan, O'Mahony, Frank, Casper, Bryan, Mooney, Randy. A Scalable 5–15 Gbps, 14–75 mW Low-Power I/O Transceiver in 65 nm CMOS. IEEE journal of solid-state circuits, vol.43, no.4, 1010-1019.

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13. Song, Young-Hoon, Bai, Rui, Hu, Kangmin, Yang, Hae-Woong, Chiang, Patrick Yin, Palermo, Samuel. A 0.47–0.66 pJ/bit, 4.8–8 Gb/s I/O Transceiver in 65 nm CMOS. IEEE journal of solid-state circuits, vol.48, no.5, 1276-1289.

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14. Park, Hwan-Wook, Lim, Hyun-Wook, Kong, Bai-Sun. Current-Integrating DFE with Sub-UI ISI Cancellation for Multi-Drop Channels. Journal of semiconductor technology and science, vol.16, no.1, 112-117.

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15. Kangmin Hu, Rui Bai, Tao Jiang, Chao Ma, Ragab, A., Palermo, S., Chiang, P. Y.. 0.16-0.25 pJ/bit, 8 Gb/s Near-Threshold Serial Link Receiver With Super-Harmonic Injection-Locking. IEEE journal of solid-state circuits, vol.47, no.8, 1842-1853.

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16. Il-Min Yi, Soo-Min Lee, Seung-Jun Bae, Young-Soo Sohn, Jung-Hwan Choi, Seong-Jin Jang, Byungsub Kim, Jae-Yoon Sim, Hong-June Park. A 40 mV-Differential-Channel-Swing Transceiver Using a RX Current-Integrating TIA and a TX Pre-Emphasis Equalizer With a CML Driver at 9 Gb/s. IEEE transactions on circuits and systems. a publication of the IEEE Circuits and Systems Society. I, Regular papers, vol.63, no.1, 122-133.

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17. IEEE ISSCC Dig Tech Papers A 3.2 Gb/s/pin 8 Gb 1.0 V LPDDR4 SDRAM with integrated ECC engine for sub-1 V DRAM core operation oh 2014 430 

18. Stojanovic, V., Ho, A., Garlepp, B.W., Chen, F., Wei, J., Tsang, G., Alon, E., Kollipara, R.T., Werner, C.W., Zerbe, J.L., Horowitz, M.A.. Autonomous dual-mode (PAM2/4) serial link transceiver with adaptive equalization and data recovery. IEEE journal of solid-state circuits, vol.40, no.4, 1012-1026.

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