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[해외논문] Effect of charge trap layer thickness on the charge spreading behavior within a few seconds in 3D charge trap flash memory

Semiconductor science and technology, v.33 no.10, 2018년, pp.10LT01 -   

Choi, Bongsik (School of Electrical Engineering, Kookmin University, Seoul 02707, Republic of Korea) ,  Lee, Jiyong (Research and Development Division, SK Hynix Semiconductor Inc., Icheon, Gyeongki 17336, Republic of Korea) ,  Yoon, Jinsu (School of Electrical Engineering, Kookmin University, Seoul 02707, Republic of Korea) ,  Jeon, Minsu (School of Electrical Engineering, Kookmin University, Seoul 02707, Republic of Korea) ,  Lee, Yongwoo (School of Electrical Engineering, Kookmin University, Seoul 02707, Republic of Korea) ,  Han, Jungmin (School of Electrical Engineering, Kookmin University, Seoul 02707, Republic of Korea) ,  Lee, Jieun (School of Electrical Engineering, Kookmin University, Seoul 02707, Republic of Korea) ,  Park, Jinhee (School of Electrical Engineering, Kookmin University, Seoul 02707, Republic of Korea) ,  Kim, Yeamin (School of Electrical Engineering, Kookmin University, Seoul 02707, Republic of Korea) ,  Kim, Dong Myong (School of Electrical Engineering, Kookmin University, Seoul 02707, Republic of Korea) ,  Kim, Dae Hwan (School of Electrical Engineering, Kookmin University, Seoul 02707, Republic of Korea) ,  Chung, Sungyong (Research and Developme) ,  Lim, Chan ,  Choi, Sung-Jin

Abstract ▼ AI-Helper 아이콘AI-Helper

Charge spreading behavior within a few seconds, referred to as early retention, was comprehensively investigated in 24 word-line stacked tube-type 3D NAND flash memory. We thoroughly explored the charge spreading behavior from the perspectives of both electron and hole spreading in 3D NAND flash mem...

참고문헌 (15)

  1. [1] Cho M K and Kim D M 2002 High performance SONOS memory cells free of drain turn-on and over-erase: compatibility issue with current flash technology IEEE Electron Device Lett. 21 399–401 High performance SONOS memory cells free of drain turn-on and over-erase: compatibility issue with current flash technology Cho M K and Kim D M IEEE Electron Device Lett. 0741-3106 21 2002 399 401 

  2. [2] Kim K 2005 Technology for sub-50nm DRAM and NAND flash manufacturing IEDM Tech. Dig. pp 323–6 Technology for sub-50nm DRAM and NAND flash manufacturing Kim K IEDM Tech. Dig. 2005 323 326 

  3. [3] Kim K and Jeong G 2007 Memory technologies for sub-40 nm node IEDM Tech. Dig. pp 27–30 Memory technologies for sub-40 nm node Kim K and Jeong G IEDM Tech. Dig. 2007 27 30 

  4. [4] Lee C-H, Choi J, Park Y, Kang C, Choi B-I, Kim H, Oh H and Lee W-S 2008 Highly scalable NAND flash memory with robust immunity to program disturbance using symmetric inversion-type source and drain structure Proc. VLSI Symp. Technol. pp 118–9 Highly scalable NAND flash memory with robust immunity to program disturbance using symmetric inversion-type source and drain structure Lee C-H, Choi J, Park Y, Kang C, Choi B-I, Kim H, Oh H and Lee W-S Proc. VLSI Symp. Technol. 2008 118 119 

  5. [5] Sim J S et al 2007 Self aligned trap-shallow trench isolation scheme for the reliability of TANOS (TaN/AlO/SiN/Oxide/Si) NAND flash memory Proc. Non-Volatile Semicond. Memory Workshop pp 110–1 Self aligned trap-shallow trench isolation scheme for the reliability of TANOS (TaN/AlO/SiN/Oxide/Si) NAND flash memory Sim J S et al Proc. Non-Volatile Semicond. Memory Workshop 2007 110 111 

  6. [6] Choi E-S and Park S-K 2012 Device considerations for high density and highly reliable 3D NAND flash cell in near future pp 211–4 Device considerations for high density and highly reliable 3D NAND flash cell in near future Choi E-S and Park S-K IEDM Tech. Dig. 0163-1918 2012 211 214 

  7. [7] Chen S-H et al 2012 A highly scalable 8-layer vertical gate 3D NAND with split-page bit line layout and efficient binary-sum MiLC (Minimal Incremental Layer Cost) staircase contacts pp 21–4 A highly scalable 8-layer vertical gate 3D NAND with split-page bit line layout and efficient binary-sum MiLC (Minimal Incremental Layer Cost) staircase contacts Chen S-H et al IEDM Tech. Dig. 0163-1918 2012 21 24 

  8. [8] Tanaka H et al 2007 Bit cost scalable technology with punch and plug process for ultra high density flash memory Proc. VLSI Symp. Technol. pp 14–5 Bit cost scalable technology with punch and plug process for ultra high density flash memory Tanaka H et al Proc. VLSI Symp. Technol. 2007 14 15 

  9. [9] Whang S et al 2010 Novel 3-dimensional dual control-gate with surrounding floating-gate (DC-SF) NAND flash cell for 1Tb file storage application IEDM Tech. Dig. pp 668–71 Novel 3-dimensional dual control-gate with surrounding floating-gate (DC-SF) NAND flash cell for 1Tb file storage application Whang S et al IEDM Tech. Dig. 2010 668 671 

  10. [10] Kang C, Choi J, Sim J, Lee C, Shin Y, Park J, Sel J, Jeon S, Park Y and Kim K 2007 Effects of lateral charge spreading on the reliability of TANOS (TaN/AlO/SiN/Oxide/Si) NAND flash memory Proc. IEEE 45th Annu. Int. Reliab. Phys. Symp. pp 167–70 Effects of lateral charge spreading on the reliability of TANOS (TaN/AlO/SiN/Oxide/Si) NAND flash memory Kang C, Choi J, Sim J, Lee C, Shin Y, Park J, Sel J, Jeon S, Park Y and Kim K Proc. IEEE 45th Annu. Int. Reliab. Phys. Symp. 2007 167 170 

  11. [11] Oh D, Lee B, Kwon E, Kim S, Cho G, Park S, Lee S and Hong S 2015 TCAD simulation of data retention characteristics of charge trap device for 3D NAND flash memory Proc. Int. Memory Workshop pp 1–4 TCAD simulation of data retention characteristics of charge trap device for 3D NAND flash memory Oh D, Lee B, Kwon E, Kim S, Cho G, Park S, Lee S and Hong S Proc. Int. Memory Workshop 2015 1 4 

  12. [12] Choi B et al 2016 Comprehensive evaluation of early retention (fast charge loss within a few seconds) characteristics in tube-type 3D NAND flash memory Proc. VLSI Symp. Technol. pp 14–6 Comprehensive evaluation of early retention (fast charge loss within a few seconds) characteristics in tube-type 3D NAND flash memory Choi B et al Proc. VLSI Symp. Technol. 2016 14 16 

  13. [13] Baik S J, Lim K S, Choi W, Yoo H, Lee J-S and Shin H 2011 Lateral redistribution of trapped charges in nitride/oxide/Si (NOS) investigated by electrostatic force microscopy Nanoscale 3 2560–5 10.1039/c1nr10104h Lateral redistribution of trapped charges in nitride/oxide/Si (NOS) investigated by electrostatic force microscopy Baik S J, Lim K S, Choi W, Yoo H, Lee J-S and Shin H Nanoscale 3 2011 2560 2565 

    상세보기 crossref

  14. [14] Chen C-P, Lue H-T, Hsieh C-C, Chang K-P, Hsieh K-Y and Lu C-Y 2010 Study of fast initial charge loss and it’s impact on the programmed states Vt distribution of charge-trapping NAND flash IEDM Tech. Dig. pp 5–6 Study of fast initial charge loss and it’s impact on the programmed states Vt distribution of charge-trapping NAND flash Chen C-P, Lue H-T, Hsieh C-C, Chang K-P, Hsieh K-Y and Lu C-Y IEDM Tech. Dig. 2010 5 6 

  15. [15] You H-W and Cho W-J 2010 Charge trapping properties of the HfO2 layer with various thicknesses for charge trap flash memory applications Appl. Phys. Lett. 96 093506 10.1063/1.3337103 Charge trapping properties of the HfO2 layer with various thicknesses for charge trap flash memory applications You H-W and Cho W-J Appl. Phys. Lett. 96 093506 2010 

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