[논문]Process Variation on Arch-structured Gate Stacked Array 3-D NAND Flash Memory

Baek, Myung-Hyun; Kim, Do-Bin; Kim, Seunghyun; Lee, Sang-Ho; Park, Byung-Gook

doi:10.5573/jsts.2017.17.2.260

[국내논문] Process Variation on Arch-structured Gate Stacked Array 3-D NAND Flash Memory 원문보기

Journal of semiconductor technology and science, v.17 no.2, 2017년, pp.260 - 264

Baek, Myung-Hyun (Electrical and Computer Engineering, Seoul National University) , Kim, Do-Bin (Electrical and Computer Engineering, Seoul National University) , Kim, Seunghyun (Electrical and Computer Engineering, Seoul National University) , Lee, Sang-Ho (Electrical and Computer Engineering, Seoul National University) , Park, Byung-Gook (Electrical and Computer Engineering, Seoul National University)

Abstract ▼ AI-Helper

Process variation effect on arch-structured gate stacked array (GSTAR) 3-D NAND flash is investigated. In case of arch-structured GSTAR, a shape of the arch channel is depending on an alignment of photo-lithography. Channel width fluctuates according to the channel hole alignment. When a shape of channel exceeds semicircle, channel width becomes longer, increasing drain current. However, electric field concentration on tunnel oxide decreases because less electric flux converges into a larger surface of tunnel oxide. Therefore, program efficiency is dependent on the process variation. Meanwhile, a radius of channel holes near the bottom side become smaller due to an etch slope. It also affects program efficiency as well as channel width. Larger hole radius has an advantage of higher drain current, but causes degradation of program speed.

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가설 설정

According to the Fig. 3(a)-(c), the more the channel is deficient to the shape of a circle, the better the program efficiency, although the on current decreases due to its shorter channel width. Fig.

제안 방법

As a results, channel width and field crowding effect is different at each wordlines (WLs). In this paper, TCAD simulation is performed to investigate the performance of arch cells according to the channel shape.

성능/효과

It is clear that the smallest case shows maximized PGM efficiency. In conclusion, WLs near the GSL shows smaller drain current and larger V_th shift with same PGM condition. Therefore, appropriate PGM scheme is required to compensate these side effects and prevent read failure.

참고문헌 (14)

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상세보기
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상세보기
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