[논문]A 10-Bit 5 MS/s VCO-SAR ADC in 0.18- <tex> $\\mu$</tex>m CMOS

Xie, Yi; Liang, Yuhua; Liu, Maliang; Liu, Shubin; Zhu, Zhangming

doi:10.1109/tcsii.2018.2833866

A 10-Bit 5 MS/s VCO-SAR ADC in 0.18- $\\mu$m CMOS

IEEE transactions on circuits and systems. a publication of the IEEE Circuits and Systems Society. II, Express briefs, v.66 no.1, 2019년, pp.26 - 30

Xie, Yi (Shaanxi Key Laboratory of Integrated Circuits and Systems, School of Microelectronics, Xidian University, Xi’an, China) , Liang, Yuhua (Shaanxi Key Laboratory of Integrated Circuits and Systems, School of Microelectronics, Xidian University, Xi’an, China) , Liu, Maliang (Shaanxi Key Laboratory of Integrated Circuits and Systems, School of Microelectronics, Xidian University, Xi’an, China) , Liu, Shubin (Shaanxi Key Laboratory of Integrated Circuits and Systems, School of Microelectronics, Xidian University, Xi’an, China) , Zhu, Zhangming (Shaanxi Key Laboratory of Integrated Circuits and Systems, School of Microelectronics, Xidian University, Xi’an, China)

Abstract ▼ AI-Helper

This brief presents a 10-bit 5 MS/s hybrid analog-to-digital converter (ADC) combining successive approximation register (SAR) with voltage-controlled oscillator (VCO) in 0.18- $\mu \text{m}$ CMOS. Non-ideal factors from practical circuit implementations are theoretically considered and modeled in Simulink. To improve the linearity and the reliability of the bootstrapped switch circuit, the body-effect compensation is adopted. The asynchronous clock generation circuit with a variable-time control cell is presented, which optimizes the DAC settling time of the MSB DAC and LSB DAC in an SAR conversion. Verilog codes and a standard digital library make it possible to synthesize the most parts of the VCO-based Nyquist ADC, greatly reducing the design costs. At Nyquist input frequency and a 5 MS/s sampling rate, a signal-to-noise and distortion ratio of 56.7 dB and a spurious-free dynamic range of 72.2 dB are achieved, respectively. The core occupies $450\,\, {\mu }{ \text{m}} {\times } {280}\,\, {\mu }\text{m}$.

참고문헌 (14)

Dai Zhang, Bhide, A., Alvandpour, A.. A 53-nW 9.1-ENOB 1-kS/s SAR ADC in 0.13- $\mu$m CMOS for Medical Implant Devices. IEEE journal of solid-state circuits, vol.47, no.7, 1585-1593.

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van Elzakker, Michiel, van Tuijl, Ed, Geraedts, Paul, Schinkel, Daniel, Klumperink, Eric, Nauta, Bram. A 10-bit Charge-Redistribution ADC Consuming 1.9 μ W at 1 MS/s. IEEE journal of solid-state circuits, vol.45, no.5, 1007-1015.

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10.1109/ISCAS.2015.7168868
Liang-Jen Chen, Shen-Iuan Liu. A 12-bit 3.4 MS/s Two-Step Cyclic Time-Domain ADC in 0.18- $\mu \text{m}$ CMOS. IEEE transactions on very large scale integration (VLSI) systems, vol.24, no.4, 1470-1483.

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Je-Kwang Cho. A 2.24-mW, 61.8-dB SNDR, 20-MS/s Pipelined ADC With Charge-Pump-Based Dynamic Biasing for Power Reduction in Op Amp Sharing. IEEE transactions on circuits and systems. a publication of the IEEE Circuits and Systems Society. I, Regular papers, vol.64, no.6, 1368-1379.

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Junfeng Gao, Guangjun Li, Letian Huang, Qiang Li. An Amplifier-Free Pipeline-SAR ADC Architecture With Enhanced Speed and Energy Efficiency. IEEE transactions on circuits and systems. a publication of the IEEE Circuits and Systems Society. II, Express briefs, vol.63, no.4, 341-345.

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10.1109/ESSCIRC.2016.7598331
Proc IEEE Symp VLSI Circuits A 18.5-fJ/step VCO-based 0–1 MASH $\Delta \Sigma $ ADC with digital background calibration sanyal 2016 26
Proc Custom Integr Circuits Conf (CICC) A hybrid SAR-VCO $\Delta \Sigma $ ADC with first-order noise shaping sanyal 2014 1
Sanyal, Arindam, Nan Sun. An Energy-Efficient Hybrid SAR-VCO $\Delta \Sigma $ Capacitance-to-Digital Converter in 40-nm CMOS. IEEE journal of solid-state circuits, vol.52, no.7, 1966-1976.

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10.1109/ISSCC.2017.7870463
Zhangming Zhu, Yuhua Liang. A 0.6-V 38-nW 9.4-ENOB 20-kS/s SAR ADC in 0.18- $\mu{\rm m}$ CMOS for Medical Implant Devices. IEEE transactions on circuits and systems. a publication of the IEEE Circuits and Systems Society. I, Regular papers, vol.62, no.9, 2167-2176.

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Liu, Chun-Cheng, Kuo, Che-Hsun, Lin, Ying-Zu. A 10 bit 320 MS/s Low-Cost SAR ADC for IEEE 802.11ac Applications in 20 nm CMOS. IEEE journal of solid-state circuits, vol.50, no.11, 2645-2654.

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Proc IEEE ISCAS A time-based analog-to-digital converter using a multi-phase voltage controlled oscillator kim 2006 3934

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A 10-Bit 5 MS/s VCO-SAR ADC in 0.18- $\\mu$m CMOS

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