Wang, Yuan
(Key Laboratory of Microelectronic Devices and Circuits (MoE), Institute of Microelectronics, Peking University, 100871, Beijing, P.R. China)
,
Liu, Yuequan
(Key Laboratory of Microelectronic Devices and Circuits (MoE), Institute of Microelectronics, Peking University, 100871, Beijing, P.R. China)
,
Jiang, Mengyin
(Key Laboratory of Microelectronic Devices and Circuits (MoE), Institute of Microelectronics, Peking University, 100871, Beijing, P.R. China)
,
Jia, Song
(Key Laboratory of Microelectronic Devices and Circuits (MoE), Institute of Microelectronics, Peking University, 100871, Beijing, P.R. China)
,
Zhang, Xing
(Key Laboratory of Microelectronic Devices and Circuits (MoE), Institute of Microelectronics, Peking University, 100871, Beijing, P.R. China)
A wide operating range and fast locking delay-locked loop (DLL) based frequency quadrupler that includes an eight-phase-clock generator and an edge combiner is proposed. The eight-phase-clock generator is composed of a coarse-code generator, a fine-code generator and a digital controlled delay line,...
A wide operating range and fast locking delay-locked loop (DLL) based frequency quadrupler that includes an eight-phase-clock generator and an edge combiner is proposed. The eight-phase-clock generator is composed of a coarse-code generator, a fine-code generator and a digital controlled delay line, which uses four differential delay units to generate equally spaced eight-phase clocks. The coarse-code generator adopts a time-to-digital scheme to achieve short locking time and wide operating range. A fine-code digital-to-analog converter in the fine-code generator converts the fine codes to analog voltage for high precision. Moreover, the novel edge-combiner circuit combines the eight-phase clocks to x4 frequency output with 50% duty cycle ratio. Experimental results in a 65-nm CMOS process show this frequency multiplier can cover a frequency range from 320 MHz to 2.4 GHz and cost 5~40 cycles to finish locking.
A wide operating range and fast locking delay-locked loop (DLL) based frequency quadrupler that includes an eight-phase-clock generator and an edge combiner is proposed. The eight-phase-clock generator is composed of a coarse-code generator, a fine-code generator and a digital controlled delay line, which uses four differential delay units to generate equally spaced eight-phase clocks. The coarse-code generator adopts a time-to-digital scheme to achieve short locking time and wide operating range. A fine-code digital-to-analog converter in the fine-code generator converts the fine codes to analog voltage for high precision. Moreover, the novel edge-combiner circuit combines the eight-phase clocks to x4 frequency output with 50% duty cycle ratio. Experimental results in a 65-nm CMOS process show this frequency multiplier can cover a frequency range from 320 MHz to 2.4 GHz and cost 5~40 cycles to finish locking.
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