[미국특허]
Method for forming capacitor of semiconductor device
원문보기
IPC분류정보
국가/구분
United States(US) Patent
공개
국제특허분류(IPC7판)
H01L-021/8238
H01L-021/20
출원번호
US-0878747
(2004-06-28)
공개번호
US-0202645
(2005-09-15)
우선권정보
KR-0016196 (2004-03-10)
발명자
/ 주소
Kim, Gyu
Yoon, Hyo
Choi, Geun
대리인 / 주소
LADAS &
인용정보
피인용 횟수 :
0인용 특허 :
0
초록▼
Disclosed is a method for forming a capacitor of a semiconductor device. An etch stop layer, first oxide layer and second oxide layer are sequentially deposited on an insulating interlayer of a substrate. Contact holes through which portions of the etch stop layer are exposed above plugs of the insu
Disclosed is a method for forming a capacitor of a semiconductor device. An etch stop layer, first oxide layer and second oxide layer are sequentially deposited on an insulating interlayer of a substrate. Contact holes through which portions of the etch stop layer are exposed above plugs of the insulating interlayer are formed. The contact holes are cleaned by a cleaning solution having an etching selectivity which is higher for the first oxide layer than for the second oxide layer, thereby enlarging lower portions of the contact holes. A spacer nitride layer is formed on surfaces of the contact holes and the second oxide layer. Portions of the spacer nitride layers located on the second oxide layer and above the plugs together with portions of the etch stop layer located on the plugs are removed. A double polysilicon layer is formed on the spacer nitride layer segments.
대표청구항▼
1. A method for forming a capacitor of a semiconductor device, the method comprising the steps of: providing a semiconductor substrate on which an insulating interlayer having plugs is formed; depositing an etch stop layer, a first oxide layer, and a second oxide layer in sequence on the insulating
1. A method for forming a capacitor of a semiconductor device, the method comprising the steps of: providing a semiconductor substrate on which an insulating interlayer having plugs is formed; depositing an etch stop layer, a first oxide layer, and a second oxide layer in sequence on the insulating interlayer; etching the second oxide layer and the first oxide layer, thereby forming contact holes through which portions of the etch stop layer above the plugs are exposed; cleaning the contact holes by a cleaning solution having an etching selectivity, which is higher for the first oxide layer than for the second oxide layer, thereby enlarging lower portions of the contact holes; forming a spacer nitride layer on surfaces of the contact holes and the second oxide layer; removing portions of the spacer nitride layers located on the second oxide layer and above the plugs together with portions of the etch stop layer located on the plugs; forming a double polysilicon layer on the spacer nitride layer segments formed on surfaces of the contact holes and on the second oxide layer, the double polysilicon layer consisting of a doped polysilicon layer and an undoped polysilicon layer stacked on each other; applying a photoresist film on the double polysilicon layer; etching back the photoresist film and the double polysilicon layer, thereby eliminating the portions of the double polysilicon layer on the second oxide layer; removing the remained photoresist film; growing hemispherical silicon grains on surfaces of segments of the undoped polysilicon layer, thereby forming lower electrodes; and forming a dielectric layer and an upper electrode in sequence on the lower electrodes. 2. The method as claimed in claim 1, wherein the first oxide layer is one selected from the group consisting of a phosphor silicate glass (PSG) film, a boro-phosphor silicate glass (BPSG) film, or an undoped silicate glass (USG) film, each containing impurities, and the second oxide layer is a tetra ethyl ortho silicate (TEOS) film containing no impurity. 3. The method as claimed in claim 1, wherein the first oxide layer has a thickness smaller than 50% of a sum of thicknesses of the first oxide layer and the second oxide layer. 4. The method as claimed in claim 1, wherein, in step 4), the contact holes are cleaned by a mixture solution of NH4OH having a concentration of 29 wt %, H2O2 having a concentration of 31 wt %, and a deionized water H2O. 5. The method as claimed in claim 4, wherein the mixture solution contains NH4OH, H2O2, and H2O mixed at a volumetric ratio of 1:1?5:20?50. 6. The method as claimed in claim 4, wherein the mixture solution containing NH4OH, H2O2, and H2O is used at a temperature between 25 and 85° C. 7. The method as claimed in claim 1, wherein, in step 4), the contact holes are cleaned by HF solution diluted with H2O or isopropyl alcohol (IPA) 8. The method as claimed in claim 7, wherein, in the HF solution diluted with H2O or IPA, the ratio of HF:H2O or HF:IPA is 1:1000?1:10. 9. The method as claimed in claim 1, wherein, in step 5), the spacer nitride layer is deposited with a thickness of 30?100 Å at a temperature between 550 and 650° C. on the surfaces of the contact holes and on the second oxide layer.
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