[미국특허]
Crosstalk-Free WLCSP Structure for High Frequency Application
원문보기
IPC분류정보
국가/구분
United States(US) Patent
공개
국제특허분류(IPC7판)
H01L-021/44
H01L-021/02
H01L-023/48
출원번호
US-0782384
(2007-07-24)
공개번호
US-0026608
(2009-01-29)
발명자
/ 주소
Tsai,Mon Chin
Yo,Hsiu Mei
Lin,Chien Min
Cheng,Chia Jen
Tseng,Li Hsin
출원인 / 주소
Tsai,Mon Chin
Yo,Hsiu Mei
Lin,Chien Min
Cheng,Chia Jen
Tseng,Li Hsin
대리인 / 주소
SLATER & MATSIL, L.L.P.
인용정보
피인용 횟수 :
0인용 특허 :
0
초록▼
A structure, a system, and a method for manufacture of crosstalk-free wafer level chip scale packaging (WLCSP) structure for high frequency applications is provided. An illustrative embodiment comprises a substrate on which various layers and structures form circuitry, a signal pin formed on the sub
A structure, a system, and a method for manufacture of crosstalk-free wafer level chip scale packaging (WLCSP) structure for high frequency applications is provided. An illustrative embodiment comprises a substrate on which various layers and structures form circuitry, a signal pin formed on the substrate and coupled with the circuitry, a ground ring encircling the signal pin, and a grounded solder bump coupled to the ground ring.
대표청구항▼
What is claimed is: 1. A crosstalk-free structure comprising: a substrate on which various layers and interconnects are formed, comprising circuitry; a signal pin formed on the substrate and coupled with the circuitry; a ground ring encircling the signal pin; and a grounded solder bump coupled to t
What is claimed is: 1. A crosstalk-free structure comprising: a substrate on which various layers and interconnects are formed, comprising circuitry; a signal pin formed on the substrate and coupled with the circuitry; a ground ring encircling the signal pin; and a grounded solder bump coupled to the ground ring. 2. The structure of claim 1, wherein the structure is implemented in a package chosen from a group consisting of a CSP (chip scaled package), a WLCSP (wafer level chip scaled package), and a flip chip package. 3. The structure of claim 1, wherein the signal pin material is chosen from a group consisting essentially of Al PPI (post passivation connection), Cu PPI, and alloys thereof. 4. The structure of claim 1, wherein the signal pin material is a Cu post structure. 5. The structure of claim 1, wherein the ground ring is an irregular shape. 6. The structure of claim 1, wherein the ground ring is a plurality of rings. 7. A system for a semiconductor device package, the system comprising: a plurality of signal pins disposed on a substrate, in which various layers and structures comprise circuitry; the plurality of signal pins coupled with the circuitry; each of the plurality of signal pins encircled with a corresponding ground ring; and each of the corresponding ground rings coupled with a grounded solder bump. 8. The system of claim 7, wherein the semiconductor device package is chosen from a group consisting of a CSP (chip scale package), a WLCSP (wafer level chip scale package), and a flip chip package. 9. The system of claim 7, wherein a signal pin material is chosen from a group consisting essentially of Al PPI (post passivation connection), Cu PPI, and alloys thereof. 10. The system of claim 7, wherein the plurality of signal pins are comprised of Cu post structures. 11. The system of claim 7, wherein the corresponding ground rings are of an irregular shape. 12. The system of claim 7, wherein the corresponding ground rings are of dissimilar shapes. 13. The system of claim 7, wherein the corresponding ground rings are chosen from a group of single rings, multiple rings, and a combination of single and multiple rings. 14. A method of manufacturing a crosstalk-free CSP (chip scale package) structure comprising: forming a patterned polyimide layer to expose a bond pad on a substrate, wherein the bond pad is coupled with underlying circuitry in the substrate; forming a metal trace layer on the substrate; patterning a photoresist layer deposited on the metal trace layer; performing an electroplating process to form a post passivation interconnection metal layer on the substrate using the metal trace layer as a seed layer, wherein the photoresist layer protects patterned areas from the electroplating process; stripping the photoresist layer and excess post passivation interconnection metal layer materials; forming a patterned second polyimide layer on the post passivation interconnection metal layer, wherein the patterned second polyimide layer defines a signal pin and a ground ring; filling the signal pin and the ground ring with a conductive material to form a coaxial structure; and performing a bump process on the substrate. 15. The method of claim 14 further comprising; polishing the substrate with a chemical mechanical polish (CMP) process, after filling the signal pin and the ground ring with the conductive material and before performing a bump process on the substrate. 16. The method of claim 14, wherein the post passivation interconnection metal layer is chosen from a group consisting essentially of Al, Cu, and alloys thereof. 17. The method of claim 14, wherein the post passivation interconnection metal layer is a Cu post structure. 18. The method of claim 14, wherein the ground ring is an irregularly shaped ring. 19. The method of claim 14, wherein the ground ring is a plurality of rings. 20. The method of claim 14, wherein the metal trace process is replaced by an under bump metallurgy process.
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