초록 ▼

A method of forming a GAA FinFET, including: forming a fin on a substrate, the substrate having a STI layer formed thereon and around a portion of a FIN-bottom portion of the fin, the fin having a dummy gate formed thereover, the dummy gate having a gate sidewall spacer on sidewalls thereof; forming

A method of forming a GAA FinFET, including: forming a fin on a substrate, the substrate having a STI layer formed thereon and around a portion of a FIN-bottom portion of the fin, the fin having a dummy gate formed thereover, the dummy gate having a gate sidewall spacer on sidewalls thereof; forming a FIN-void and an under-FIN cavity in the STI layer; forming first spacers by filling the under-FIN cavity and FIN-void with a first fill; removing the dummy gate, thereby exposing both FIN-bottom and FIN-top portions of the fin underneath the gate; creating an open area underneath the exposed FIN-top by removing the exposed FIN-bottom; and forming a second spacer by filling the open area with a second fill; wherein a distance separates a top-most surface of the second spacer from a bottom-most surface of the FIN-top portion. A GAA FinFET formed by the method is also disclosed.

대표청구항 ▼

1. A gate-all-around (GAA) FinFET comprising: a substrate having at least one bi-layer fin formed thereon;a shallow trench isolation (STI) layer formed on the substrate and around a portion of a FIN-bottom portion of the bi-layer fin;a high-k metal gate (HKMG) around a FIN-top portion of the bi-laye

1. A gate-all-around (GAA) FinFET comprising: a substrate having at least one bi-layer fin formed thereon;a shallow trench isolation (STI) layer formed on the substrate and around a portion of a FIN-bottom portion of the bi-layer fin;a high-k metal gate (HKMG) around a FIN-top portion of the bi-layer fin, the HKMG not touching any portion of the substrate and the HKMG having a gate sidewall spacer formed on sidewalls thereof;at least two first spacers composed of a first fill, one first spacer being in the STI layer and not underneath the HKMG and the gate sidewall spacer, another first spacer being in the STI layer and underneath the gate sidewall spacer but not underneath the HKMG;a second spacer composed of a second fill, the second spacer being in the STI layer and underneath the HKMG and the FIN-top portion of the fin, a top surface of the second spacer being in contact with a bottom surface of the HKMG; anda source adjacent to a first sidewall of the FIN-top portion and a drain adjacent to a second sidewall of the FIN-top portion, the second sidewall being opposite to the first sidewall, the source and the drain being above the STI layer and the first spacers and not touching any portion of the substrate;wherein a distance separates a top-most surface of the second spacer from a bottom-most surface of the FIN-top portion. 2. The GAA FinFET of claim 1, further comprising a first interlayer dielectric (ILD) layer formed on the source and drain, the first ILD layer having a top surface below a top surface of the HKMG. 3. The GAA FinFET of claim 2, further comprising a second ILD layer formed on the first ILD layer. 4. The GAA FinFET of claim 1, wherein the distance that separates the top-most surface of the second spacer from the bottom-most surface of the FIN-top portion is in a range of from about 15 nanometers to about 30 nanometers. 5. The GAA FinFET of claim 1, wherein a height of the first spacer underneath the gate sidewall spacer but not underneath the HKMG is greater than a height of the first spacer not underneath the HKMG and the gate sidewall spacer. 6. The GAA FinFET of claim 1, wherein at least one of the first and second spacers have a bottom-most width greater than a top-most width. 7. The GAA FinFET of claim 1, wherein the first fill is a material selected from a group consisting of SiN, SiON, SiBCN and SiOCN. 8. The GAA FinFET of claim 1, wherein the second fill is a material selected from a group consisting of SiO2 and SiCO. 9. The GAA FinFET of claim 1, wherein the second spacer has a height from a top-most surface of the substrate that is smaller than a height of the first spacer underneath the gate sidewall spacer but not underneath the HKMG. 10. The GAA FinFET of claim 1, wherein at least one of the first and second spacers contain an air gap enclosed thereby.