A duty cycle correction circuit is provided. The duty cycle correction circuit may include a correction circuit configured to correct a duty cycle of an external clock signal according to a locking signal. The duty cycle correction circuit may include a locking signal detection circuit configured to
A duty cycle correction circuit is provided. The duty cycle correction circuit may include a correction circuit configured to correct a duty cycle of an external clock signal according to a locking signal. The duty cycle correction circuit may include a locking signal detection circuit configured to generate the locking signal for correcting the duty cycle of the external clock signal, using an internal clock signal generated in a semiconductor circuit.
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1. A duty cycle correction circuit comprising: a correction circuit configured to correct a duty cycle of an external clock signal according to a locking signal; anda locking signal detection circuit configured to generate the locking signal for correcting the duty cycle of the external clock signal
1. A duty cycle correction circuit comprising: a correction circuit configured to correct a duty cycle of an external clock signal according to a locking signal; anda locking signal detection circuit configured to generate the locking signal for correcting the duty cycle of the external clock signal, using an internal clock signal generated in a semiconductor circuit,wherein the internal clock signal is generated independently of the external clock signal. 2. The duty cycle correction circuit according to claim 1, wherein the external clock signal comprises a single-phase clock signal provided from outside the semiconductor circuit. 3. The duty cycle correction circuit according to claim 1, wherein the internal clock signal comprises differential clock signals. 4. The duty cycle correction circuit according to claim 1, wherein the correction circuit comprises: a receiver configured to receive the external clock signal according to a reference voltage;an integrator configured to integrate an output signal of the receiver and output an output signal including the integration result;a comparator configured to generate a comparison signal by comparing the locking signal and the output signal of the integrator; anda duty cycle calibrator configured to calibrate the duty cycle of the external clock signal according to the comparison signal. 5. The duty cycle correction circuit according to claim 1, wherein the locking signal detection circuit is enabled until duty locking is completed after duty locking is started, and disabled after the duty locking is completed. 6. The duty cycle correction circuit according to claim 1, wherein the locking signal detection circuit comprises: an oscillator configured to generate internal differential clock signals;a buffer configured to buffer the internal differential clock signals and generate output signals including the buffered signals;a duty cycle detector configured to generate differential duty detection signals by detecting a duty difference between the output signals of the buffer;a duty cycle calibrator configured to calibrate duty cycles of the internal differential clock signals according to the differential duty detection signals; anda locking signal detector configured to output a level at which the duty locking of the internal differential clock signals is completed, as the locking signal. 7. The duty cycle correction circuit according to claim 6, wherein the locking signal detector comprises: an analog to digital converter configured to generate differential duty detection codes by converting the differential duty detection signals into digital signals;a code comparator configured to determine whether the values of the differential duty detection codes coincide with each other, and activate a transmission enable signal; anda locking signal transmitter configured to output any one of the differential duty detection signals as the locking signal, when the transmission enable signal is activated. 8. The duty cycle correction circuit according to claim 7, wherein the analog to digital converter comprises: a divider resistor configured to generate a plurality of reference voltages by dividing a voltage level between a power supply terminal and a ground terminal through a plurality of resistors;a plurality of first comparators configured to generate any one of the differential duty detection codes by comparing any one of the differential duty detection signals to the respective reference voltages; anda plurality of second comparators configured to generate the other of the differential duty detection codes by comparing the other of the differential duty detection signals to the respective reference voltages. 9. The duty cycle correction circuit according to claim 7, wherein the code comparator comprises: a plurality of logic gates configured to receive the differential duty detection codes by a pair of bits in the same order, and generate output signals by performing a first logic operation on the received signals; andan operation logic configured to generate the transmission enable signal by performing a second logic operation on the output signals of the plurality of logic gates. 10. The duty cycle correction circuit according to claim 6, further comprising an enable control circuit configured to enable the locking signal detection circuit until the duty locking is completed after duty calibration is started, and disable the locking signal detection circuit after the duty locking is completed. 11. The duty cycle correction circuit according to claim 10, wherein the enable control circuit performs an OR operation on a calibration end signal and the locking signal. 12. The duty cycle correction circuit according to claim 11, wherein the calibration end signal is generated according to a duty calibration command. 13. The duty cycle correction circuit according to claim 1, wherein the correction circuit comprises: a receiver configured to receive the external clock signal according to a reference voltage;a repeater configured to retransmit an output signal of the receiver to predetermined circuit components in a semiconductor circuit;an integrator configured to integrate an output signal of the repeater and output an output signal including the integration result;a comparator configured to generate differential comparison codes by comparing the locking signal and the output signal of the integrator; anda first duty cycle calibrator configured to calibrate the duty cycle of the external clock signal according to the differential comparison codes. 14. The duty cycle correction circuit according to claim 13, wherein the first duty cycle calibrator comprises: an inverter having an input terminal coupled to the receiver;a plurality of pull-up legs coupled between a power supply terminal and the inverter in common, and configured to pull up an output node of the inverter, using drivability varied through legs which are selectively turned on according to the differential comparison codes; anda plurality of pull-down legs coupled between a ground terminal and the inverter in common, and configured to pull down the output node of the inverter, using drivability varied through legs which are selectively turned on according to the differential comparison codes. 15. The duty cycle correction circuit according to claim 13, wherein the locking signal detection circuit comprises: an oscillator configured to generate internal differential clock signals;a buffer configured to buffer the internal differential clock signals and generated output signals including the buffered signals;a replica configured to delay the output signals of the buffer by the same delay time as a signal processing delay time of the repeater, and output the delayed signals;a duty cycle detector configured to generate differential duty detection codes by detecting a duty difference between the output signals of the replica;a second duty cycle calibrator configured to calibrate duty cycles of the internal differential clock signals according to the differential duty detection codes; anda locking signal detector configured to output a level at which the duty locking of the internal differential clock signals is completed, as the locking signal. 16. A duty cycle correction circuit comprising: a repeater configured to retransmit a received external clock signal to predetermined circuit components in a semiconductor circuit;a comparator configured to generate a comparison signal by comparing a locking signal and the output signal of the repeater;a first duty cycle calibrator configured to adjust a duty cycle of the external clock signal according to the comparison signal;an oscillator configured to generate internal differential clock signals;a replica configured to delay the internal differential clock signals by the same delay time as a signal processing delay time of the repeater, and output signals including the delayed signals;a duty cycle detector configured to generate differential duty detection signals by detecting a duty difference between the output signals of the replica;a second duty cycle calibrator configured to calibrate the duty cycles of the internal differential clock signals according to the differential duty detection signals; anda locking signal detector configured to output a level at which the duty locking of the internal differential clock signals is completed, as the locking signal. 17. The duty cycle correction circuit according to claim 16, wherein the duty cycle detector comprises: an amplifier circuit configured to receive the differential output signals of the replica, and output amplified differential duty detection signals; andan analog to digital converter configured to convert the differential duty detection signals into digital differential duty detection codes. 18. The duty cycle correction circuit according to claim 16, wherein the locking signal detector comprises: a code comparator configured to determine whether the values of the differential duty detection codes coincide with each other, and activate a transmission enable signal; anda locking signal transmitter configured to output any one of the differential duty detection codes as the locking signal, when the transmission enable signal is activated. 19. The duty cycle correction circuit according to claim 18, wherein the code comparator comprises: a plurality of logic gates configured to receive the differential duty detection codes by a pair of bits in the same order, and generate output signals by performing a first logic operation on the received signals; andan operation logic configured to generate the transmission enable signal by performing a second logic operation on the output signals of the plurality of logic gates. 20. The duty cycle correction circuit according to claim 16, further comprising an enable control circuit configured to enable the locking signal detection circuit until the duty locking is completed after duty calibration is started, and disable the locking signal detection circuit after the duty locking is completed.
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