EMBEDDED MEMORY DEVICE WITH REDUCED PLASMA-INDUCED DAMAGE AND METHODS OF FORMING THE SAME
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IPC분류정보
국가/구분
United States(US) Patent
공개
국제특허분류(IPC7판)
H01L-023/60
H10B-053/30
H10B-061/00
H10B-063/00
출원번호
18303631
(2023-04-20)
공개번호
20240113043
(2024-04-04)
발명자
/ 주소
Chuang, Harry-Hak-Lay
Wang, Hung Cho
You, Wen-Chun
출원인 / 주소
Chuang, Harry-Hak-Lay
인용정보
피인용 횟수 :
0인용 특허 :
0
초록▼
A semiconductor device and methods of fabrication thereof including a substrate, a doped well formed in the substrate, a transistor formed on the substrate, a dielectric material located over the doped well and the transistor and including interconnect structures extending through the dielectric mat
A semiconductor device and methods of fabrication thereof including a substrate, a doped well formed in the substrate, a transistor formed on the substrate, a dielectric material located over the doped well and the transistor and including interconnect structures extending through the dielectric material, the interconnect structures including a first set of interconnect structures electrically coupled to an active region of the transistor and a second set of interconnect structures electrically coupled to the doped well, an active memory cell electrically coupled to the active region of the transistor via the first set of interconnect structures; and a dummy memory cell electrically coupled to the doped well via the second set of conductive interconnect structures. The dummy memory cell and the second set of conductive interconnect structures may provide a low resistance pathway for plasma charge to flow to the doped well, thereby minimizing plasma induced damage to the transistor.
대표청구항▼
1. A semiconductor device, comprising: a substrate comprising a semiconductor material layer;a doped well formed in the semiconductor material layer of the substrate;a transistor formed on the substrate;a dielectric material located over the doped well and the transistor and including conductive int
1. A semiconductor device, comprising: a substrate comprising a semiconductor material layer;a doped well formed in the semiconductor material layer of the substrate;a transistor formed on the substrate;a dielectric material located over the doped well and the transistor and including conductive interconnect structures extending through the dielectric material, wherein the conductive interconnect structures comprise a first set of one or more conductive interconnect structures electrically coupled to an active region of the transistor and a second set of one or more conductive interconnect structures electrically coupled to the doped well;an active memory cell contacting the dielectric material and electrically coupled to the active region of the transistor via the first set of one or more conductive interconnect structures; anda dummy memory cell contacting the dielectric material and electrically coupled to the doped well via the second set of one or more conductive interconnect structures. 2. The semiconductor device of claim 1, wherein the doped well is doped with dopants of a first conductivity type, and the active region comprises a portion of the semiconductor material layer of the substrate that is doped with dopants of a second conductivity type that is opposite the first conductivity type. 3. The semiconductor device of claim 2, wherein the active memory cell and the dummy memory cell each comprise: a lower contact via contacting an upper surface of a metal line;a memory element contacting an upper surface of the lower contact via; andan upper contact via contacting an upper surface of the memory element, wherein the dielectric material laterally surrounds each of the active memory cell and the dummy memory cell. 4. The semiconductor device of claim 1, wherein the active memory cell and the dummy memory cell each comprise a magnetoresistive random-access memory (MRAM) memory cell, a resistive random-access memory (RRAM) memory cell, a conductive-bridge random-access memory (CBRAM) memory cell, or a ferroelectric random-access memory (FeRAM) memory cell. 5. The semiconductor device of claim 1, further comprising: an additional dummy memory cell contacting the dielectric material and electrically isolated from the transistor and the substrate. 6. The semiconductor device of claim 5, wherein the additional dummy memory cell contacts an upper surface of a metal line that is surrounded on its lateral side surfaces and its lower surface by the dielectric material. 7. The semiconductor device of claim 5, wherein the additional dummy memory cell is located between the dummy memory cell and the active memory cell. 8. The semiconductor device of claim 7, wherein the conductive interconnect structures comprise a third set of one or more conductive interconnect structures electrically coupled to a gate electrode of the transistor, the third set of one or more conductive interconnect structures comprising a word line extending continuously along one side of the dummy memory cell, the additional dummy memory cell and the active memory cell and is separated from the dummy memory cell, the additional dummy memory cell and the active memory cell by the dielectric material. 9. The semiconductor device of claim 8, wherein the transistor comprises: a first active region that is electrically coupled to the active memory cell by the first set of one or more conductive interconnect structures;a pair of gate electrodes on either side of the first active region that are electrically coupled to the word line via the third set of one or more conductive interconnect structures; anda pair of second active regions, each of the gate electrodes of the pair of gate electrodes located between the first active region and a respective second active region of the pair of second active regions. 10. The semiconductor device of claim 9, wherein the conductive interconnect structures further comprise a source line extending continuously within the dielectric material in a direction perpendicular to the word line, the source line electrically coupled to the pair of second active regions of the transistor via a pair of metal contact vias. 11. A semiconductor device, comprising: a substrate comprising a semiconductor material layer;a plurality of access transistors formed on the substrate;at least one doped well formed in the semiconductor material layer of the substrate adjacent to the plurality of access transistors;a plurality of active memory cells, each active memory cell electrically coupled to an active region of an access transistor via a first set of one or more conductive interconnect structures;a plurality of first dummy memory cells, each first dummy memory cell electrically isolated from the substrate and the access transistors; anda plurality of second dummy memory cells, each second dummy memory cell electrically coupled to a doped well via a second set of one or more conductive interconnect structures. 12. The semiconductor device of claim 11, further comprising: a contact-level structure over the substrate and the plurality of access transistors comprising a first dielectric material layer and a plurality of contact vias within the first dielectric material layer; andone or more interconnect-level structures over the contact-level structure, each interconnect-level structure comprising: a dielectric material layer; andconductive interconnect structures in the dielectric material layer, wherein the plurality of active memory cells, the plurality of first dummy memory cells and the plurality of second dummy memory cells are located within an interconnect-level structure and are laterally-surrounded by a dielectric material layer. 13. The semiconductor device of claim 12, wherein the contact-level structure comprises: a plurality of first contact vias electrically contacting respective first active regions of the access transistors;a plurality of second contact vias structures electrically contacting respective second active regions of the access transistors;a plurality of third contact vias electrically contacting respective gate electrodes of the access transistors; anda plurality of fourth contact vias electrically contacting a doped well, and the one or more interconnect-level structures comprises a first interconnect-level structure over the contact-level structure, the first interconnect-level structure comprising: a second dielectric material layer;a first metal line extending continuously along a first horizontal direction and electrically contacting each of the first contact vias of the contact-level structure;a plurality of second metal lines and metal vias contacting an upper surface of each of the second metal lines, each of the second metal lines electrically contacting a second contact via of the contact-level structure;a plurality of third metal lines and metal vias contacting an upper surface of each of the third metal lines, each of the third metal lines electrically contacting a pair of third contact vias of the contact-level structure; anda fourth metal line extending continuously along the first horizontal direction and electrically contacting each of the fourth contact vias of the contact-level structure. 14. The semiconductor device of claim 13, wherein the one or more interconnect-level structures comprises a second interconnect-level structure over the first interconnect-level structure, the second interconnect-level structure comprising: a third dielectric material layer;a plurality of first metal lines, each of the first metal lines of the second interconnect-level structure electrically coupled to a second metal line of the first interconnect-level structure by a metal via of the first-interconnect structure;a plurality of second metal lines, each of the second metal lines comprising a strip-shaped portion extending continuously along a second horizontal direction that is perpendicular to the first horizontal direction and at least one protruding portion that protrudes from a side of the strip-shaped portion along the first horizontal direction, each of the protruding portions of the second metal lines of the second interconnect-level structure electrically coupled to a third metal line of the first interconnect-level structure by a metal via of the first interconnect-level structure; anda plurality of third metal lines, each of the third metal lines of the second interconnect-level structure electrically coupled to a fourth metal line of the first interconnect-level structure by a metal via of the first-interconnect structure, and the second interconnect-level structure further comprises a plurality of metal vias, wherein at least one of the metal vias contacts an upper surface of each of the first metal lines, the strip-shaped portion of the second metal lines, and the third metal lines of the second interconnect-level structure. 15. The semiconductor device of claim 14, wherein the one or more interconnect-level structures comprises: a third interconnect-level structure over the second interconnect-level structure, the third interconnect-level structure comprising: a fourth dielectric material layer;a plurality of first metal lines, each of the first metal lines of the third interconnect-level structure electrically coupled to a first metal line of the second interconnect-level structure by a metal via of the second-interconnect structure;a plurality of second metal lines, each of the second metal lines of the third interconnect-level structure at least partially overlying a protruding portion of a second metal line of the second interconnect-level structure;a plurality of third metal lines, each of the third metal lines of the third interconnect-level structure electrically coupled to a third metal line of the second interconnect-level structure by a metal via of the second-interconnect structure; anda plurality of fourth metal lines extending continuously along the second horizontal direction, each of the fourth metal lines of the third interconnect-level structure electrically coupled to a strip-shaped portion of a second metal line of the second interconnect-level structure by at least one metal via of the second interconnect-level structure. 16. The semiconductor device of claim 15, wherein: each of the active memory cells comprises a lower contact via contacting the upper surface of a first metal line of the third interconnect-level structure, a memory element over the lower contact via, and an upper contact via over the memory element;each of the first dummy memory cells comprises a lower contact via contacting the upper surface of a second metal line of the third interconnect-level structure, a memory element over the lower contact via, and an upper contact via over the memory element; andeach of the second dummy memory cells comprises a lower contact via contacting the upper surface of a third metal line of the third interconnect-level structure, a memory element over the lower contact via, and an upper contact via over the memory element. 17. A method of fabricating a semiconductor device, comprising: forming a doped well in a semiconductor material layer of a substrate;forming a transistor on the substrate;forming a dielectric material over the transistor and the doped well and a plurality of conductive interconnect structures within the dielectric material, the plurality of interconnect structures including a first set of one or more conductive interconnect structures electrically coupled to an active region of the transistor and a second set of one or more conductive interconnect structures electrically coupled to the doped well; andforming an active memory cell and a dummy memory cell over the dielectric material and the plurality of conductive interconnect structures, wherein the active memory cell is electrically coupled to the active region of the transistor via the first set of one or more conductive interconnect structures, and the dummy memory cell is electrically coupled to the doped well via the second set of one or more conductive interconnect structures. 18. The method of claim 17, further comprising forming an additional dummy memory cell over the dielectric material and the plurality of interconnect structures, wherein the additional dummy memory cell is electrically isolated from the transistor and the substrate. 19. The method of claim 18, wherein forming the active memory cell, the dummy memory cell and the additional dummy memory cell comprises: etching the dielectric material through a patterned mask to form a plurality of via openings in the dielectric material;depositing a conductive material within the via openings to form a plurality of lower contact vias;depositing a continuous bottom electrode layer over the dielectric material and the plurality of lower contact vias;depositing a continuous memory material layer over the continuous bottom electrode layer;depositing a continuous top electrode layer over the continuous memory material layer;etching the continuous top electrode layer, the continuous memory material layer, and the continuous bottom electrode layer to form a plurality of discrete memory elements contacting respective lower contact vias;depositing additional dielectric material over side surfaces and upper surfaces of the discrete memory elements;etching the additional dielectric material through a patterned mask to form a plurality of via openings in the additional dielectric material; anddepositing a conductive material within the via openings to form a plurality of upper contact vias contacting each of the discrete memory elements. 20. The method of claim 19, wherein at least one of the deposition steps or the etching steps used to form the active memory cell, the dummy memory cell and the additional dummy memory cell comprises a plasma-assisted deposition or etching process.
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