초록 ▼

A focal plane array, comprised of an infrared (IR) photovoltaic detector array coupled to a charge coupled device (CCD), which provides for minimum deviation in input threshold voltage between individual detector input nodes of the array is disclosed. In one embodiment, an oxide nitride dielectric l

A focal plane array, comprised of an infrared (IR) photovoltaic detector array coupled to a charge coupled device (CCD), which provides for minimum deviation in input threshold voltage between individual detector input nodes of the array is disclosed. In one embodiment, an oxide nitride dielectric layer overlays the entire CCD with the exception of the areas beneath the direct injection gates where only a thin oxide dielectric is formed. In another embodiment, the oxide beneath the direct injection gates is substantially thinner than the oxide beneath the remainder of the CCD structure.

대표청구항 ▼

In a focal plane array having a plurality of commonly connected photodetectors and a plurality of charge coupled devices (CCD\s) arranged in rows and columns coupled to respective detectors, each of said CCD\s including transfer and direct injection input gates overlaying an inner surface of a semic

In a focal plane array having a plurality of commonly connected photodetectors and a plurality of charge coupled devices (CCD\s) arranged in rows and columns coupled to respective detectors, each of said CCD\s including transfer and direct injection input gates overlaying an inner surface of a semiconductive substrate facing the detectors, each of said input gates being commonly connected for the application of a bias voltage during operation, and whereby photocurrent commences to flow into each CCD upon the application of a voltage of minimum threshold value to its respective input gate, the improvement of a dielectric layer having first portions sandwiched between the inner surface of the substrate and opposing surfaces of each of the input gates, said dielectric layer having second portions sandwiched between the inner surface of the substrate and opposing surfaces of the transfer gates, said sandwiched first portions directly beneath each of the input gates being of a thickness between approximately 80 and 200 Angstroms to improve the uniformity of the threshold voltage between individual input gates, said sandwiched second portions directly beneath the transfer gates being thicker than the portions directly beneath each of the input gates, said second portions being of sufficient thickness to prevent dielectric breakdown of the dielectric during clocking operation of the CCD.