A bit-serial pipeline Galois Field Multiplier for multiplying an element K(X)=Km-1Xm-1+Km-2Xm-2 Xm-2+. . . +K0 with another element Y(X)=Ym-1 Xm-1+Ym-2 Xm-2+. . . +Y0 to obtain Z0=Zm-1 Xm-1+Zm-2 Xm-2+. . . +Z0, which is also an element of the field generally defined by P(X)=amXm+am-1 Xm-1+am-2 Xm-2+
A bit-serial pipeline Galois Field Multiplier for multiplying an element K(X)=Km-1Xm-1+Km-2Xm-2 Xm-2+. . . +K0 with another element Y(X)=Ym-1 Xm-1+Ym-2 Xm-2+. . . +Y0 to obtain Z0=Zm-1 Xm-1+Zm-2 Xm-2+. . . +Z0, which is also an element of the field generally defined by P(X)=amXm+am-1 Xm-1+am-2 Xm-2+. . . a1X+a0. The multiplier has an input shift register buffer circuit, an intermediate shift register circuit, an output shift register circuit and multiplying and summing device. The input shift register buffer circuit is configured for serially receiving the K(X) coefficients. The multiplying and summing device receives arrangements of K(X) coefficients and the Y(X) coefficients and operates thereon, by multiplying corresponding pairs of register stage elements and Y(X) coefficients and summing the products. The output shift register circuit receives the resulting coefficients and, beginning m clock intervals after the inputting of K(X) and Y(X) coefficients is started, starts continuous outputing of the product coefficients Zm-1, Zm-2, . . . ,Z0.
대표청구항▼
A pipeline Galois Field (2m) multiplier for multiplying elements of a finite field, represented by factors K(X) and Y(X), to obtain a product Z(X), wherein K(X) has the form K(X)=Km-1Xm-1+Km-2Xm-2+. . . +K0, Y(X) has the form Y(X)=Ym-1Xm-1+Ym-2Xm-2+. . . +Yo and Z(X) has the form Z(X)=Zm-1m-1+Zm-2Xm
A pipeline Galois Field (2m) multiplier for multiplying elements of a finite field, represented by factors K(X) and Y(X), to obtain a product Z(X), wherein K(X) has the form K(X)=Km-1Xm-1+Km-2Xm-2+. . . +K0, Y(X) has the form Y(X)=Ym-1Xm-1+Ym-2Xm-2+. . . +Yo and Z(X) has the form Z(X)=Zm-1m-1+Zm-2Xm-2+. . . +Zo, said multiplier apparatus comprising: (a) a serial in, parallel out input shaft register buffer circuit having m serially arranged register stages Rm-1, Rm-2, . . . , R0 and being connected for serially receiving the K(X) coefficients Km-1, Km-2, . . . , K0; (b) computer means connected for receiving, in parallel, at a preselected clock pulse, the contents of the Rm-l, Rm-2, . . . , R0 register stages of the initiating register circuit and for serially receiving the Y(X) coefficients Ym-1, Ym-2, . . . , Y0, and for operating thereon to provide an intermediate series of m logic functions Si=fm-1Ym-1+fm-2Ym-2+. . . +f0Y0, wherein fm-1, fm-2, . . . , f0 are functions of Km-1, Km-2, . . . , K0; (c) a serial in serial out output shift register circuit having m serial arranged shift register stages Rm-1″, Rm-2″, . . . , R0″and being connected for serially receiving the series of m logic functions Si from the computing means and, in response thereto, providing a serial output of Z(X) product coefficients Zm-1, Zm-2, . . . , Z0; and (d) timing means for providing clock pulses to the input and output shift register circuits and to the computing means for synchronizing the operation thereof.
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