초록 ▼

A floating current source comprising two identically sized field effect transistors, one defining a reference transistor and the other defining a floating output transistor. The reference transistor has its gate connected to a reference voltage and its source connected to receive an input current fr

A floating current source comprising two identically sized field effect transistors, one defining a reference transistor and the other defining a floating output transistor. The reference transistor has its gate connected to a reference voltage and its source connected to receive an input current from an input current source and to generate a gate-to-source voltage which when applied as a gate-to-source voltage of the floating output transistor will generate an output current in the output transistor equal to the input current. Circuit means are included for applying between the gate and source of the output transistor a voltage equal to the gate-to-source drain voltage of the reference transistor.

대표청구항 ▼

A floating current source, comprising: two field effect transistors FET\s, one of said FETs defining a reference FET (FET-R) and the other defining a floating output FET, FET-O; FET-R having its gate connected to a reference voltage VR, and its source connected to receive an input current from an in

A floating current source, comprising: two field effect transistors FET\s, one of said FETs defining a reference FET (FET-R) and the other defining a floating output FET, FET-O; FET-R having its gate connected to a reference voltage VR, and its source connected to receive an input current from an input current source and to generate a gate-to-source voltage which when applied as a gate-to-source voltage to FET-O will generate an output current in FET-O equal to the input current or a multiple thereof; and circuit means for applying source of FET-O a voltage equal to the gate-to-source voltage of FET-R, including a series circuit having two matching resistors, R1 and R2, means for generating a voltage V1 across R1 substantially equal to the gate-to-source voltage at FET-R, means for generating a substantially equal voltage V2 across R2, and means for applying V2 across the gate and source of FET-O.