IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0978650
(2007-10-30)
|
등록번호 |
US-7508265
(2009-03-24)
|
우선권정보 |
TW-95141606 A(2006-11-10) |
발명자
/ 주소 |
|
출원인 / 주소 |
- Orise Technology Co., Ltd.
|
대리인 / 주소 |
Muncy, Geissler, Olds & Lowe, PLLC
|
인용정보 |
피인용 횟수 :
4 인용 특허 :
7 |
초록
▼
A rail-to-rail class-AB operational amplifier includes a first differential pair unit for receiving a pair of differential signals and generating a first control signal; a second differential pair unit for receiving the pair of differential signals and generating a second control signal; and an outp
A rail-to-rail class-AB operational amplifier includes a first differential pair unit for receiving a pair of differential signals and generating a first control signal; a second differential pair unit for receiving the pair of differential signals and generating a second control signal; and an output stage for receiving the first control signal and the second control signal and then generating an output voltage. The first differential pair unit includes a first active load, a first transistor differential pair and a first current source. The second differential pair unit includes a second current source, a second transistor differential pair and a second active load. The output stage includes a third current source, a fourth current source and a parallel transistor pair disposed between a second terminal of the third current source and a first terminal of the fourth current source, a first output transistor and a second output transistor, and generates the output voltage according to the first control signal and the second control signal.
대표청구항
▼
What is claimed is: 1. A rail-to-rail class-AB operational amplifier, comprising: a first differential pair unit, for receiving a pair of differential signals and generating a first control signal; a second differential pair unit, for receiving the pair of differential signals and generating a seco
What is claimed is: 1. A rail-to-rail class-AB operational amplifier, comprising: a first differential pair unit, for receiving a pair of differential signals and generating a first control signal; a second differential pair unit, for receiving the pair of differential signals and generating a second control signal; and an output stage, for receiving the first control signal and the second control signal and then generating an output voltage, wherein: the first differential pair unit includes: a first active load, having one terminal connected to an operation voltage; a first transistor differential pair, having gates for respectively receiving the pair of differential signals, drains connected to the first active load and sources connected to each other; and a first current source, having one terminal connected to the sources of the first transistor differential pair, and the other terminal grounded; the second differential pair unit includes: a second current source, having one terminal connected to the operation voltage; a second transistor differential pair, having gates for receiving the differential signals, and sources connected to each other and to the other terminal of the second current source; and a second active load, having one terminal connected to the second transistor differential pair, and the other terminal grounded; and the output stage includes: a third current source, having a first terminal connected to the operation voltage and a second terminal for receiving the first control signal; a fourth current source, having a first terminal for receiving the second control signal, and a second terminal grounded; a parallel transistor pair, which is disposed between the second terminal of the third current source and the first terminal of the fourth current source, and has gates for respectively receiving a pair of bias voltages; a first output transistor, having a source connected to the operation voltage, a gate for receiving the first control signal and a drain for generating the output voltage; and a second output transistor, having a source grounded, a gate for receiving the second control signal and a drain connected to the drain of the first output transistor. 2. The operational amplifier according to claim 1, wherein the first current source is a transistor. 3. The operational amplifier according to claim 1, wherein the second current source is a transistor. 4. The operational amplifier according to claim 1, wherein the third current source is a transistor. 5. The operational amplifier according to claim 1, wherein the fourth current source is a transistor. 6. The operational amplifier according to claim 1, wherein the first active load comprises: a first load transistor, having a source connected to the operation voltage, and a gate and a drain both connected to each other and to the drain of a transistor of the first transistor differential pair; and a second load transistor, having a source connected to the operation voltage, a gate connected to the gate of the first load transistor and a drain connected to the drain of the other transistor of the first transistor differential pair. 7. The operational amplifier according to claim 1, wherein the second active load comprises: a first load transistor, having a source grounded, and a gate and a drain both connected to each other and to the drain of one transistor of the second transistor differential pair; and a second load transistor, having a source grounded, a gate connected to the gate of the first load transistor and a drain connected to the drain of the other transistor of the second transistor differential pair. 8. The operational amplifier according to claim 1, wherein the first active load comprises: a first load transistor, having a source connected to the operation voltage; a second load transistor, having a source connected to a drain of the first load transistor, a gate connected to a gate of the first load transistor, and a drain connected to the gate of the second load transistor and to the drain of one transistor of the first transistor differential pair; a third load transistor, having a source connected to the operation voltage, and a gate connected to the gate of the first load transistor; and a fourth load transistor, having a source connected to a drain of the third load transistor, a gate connected to the gate of the third load transistor, and a drain connected to the drain of the other transistor of the first transistor differential pair. 9. The operational amplifier according to claim 1, wherein the second active load comprises: a first load transistor, having a source grounded; a second load transistor, having a source connected to a drain of the first load transistor, a gate connected to a gate of the first load transistor, and a drain connected to the gate of the second load transistor and the drain of one transistor of the second transistor differential pair; a third load transistor, having a source grounded, and a gate connected to the gate of the first load transistor; and a fourth load transistor, having a source connected to a drain of the third load transistor, a gate connected to the gate of the third load transistor and a drain connected to the drain of the other transistor of the second transistor differential pair.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.