$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

[미국특허] Semiconductor package 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H05H-007/20
출원번호 US-0332912 (1989-04-04)
발명자 / 주소
  • Butt Sheldon H. (Godfrey IL)
출원인 / 주소
  • Olin Corporation (New Haven CT 02)
인용정보 피인용 횟수 : 91  인용 특허 : 16

초록 ▼

A semiconductor package for mounting a chip is disclosed. The package includes a first metal or metal alloy component having a first thin refractory oxide layer on a first surface. The chip is bonded to the first component. A skirt extends from the first component for strengthening the first compone

대표청구항 ▼

A semiconductor package for mounting a chip comprising: a substrate member having inner and outer surfaces with sides disposed therebetween, said inner surface adapted for mounting the chip thereon; a lead frame disposed adjacent to at least one side of said substrate, said lead frame comprised of i

이 특허에 인용된 특허 (16) 인용/피인용 타임라인 분석

  1. Butt Sheldon H. (Godfrey IL), Casing for an electrical component having improved strength and heat transfer characteristics.
    상세보기
  2. Andrews Daniel M. (San Marcos CA) Merlina Joseph F. (Harrisburg PA) Redmond John P. (Mechanicsburg PA) Scheingold William S. (Palmyra PA) Ulbrich George (Harrisburg PA), Chip carrier.
    상세보기
  3. Morris ; Sr. James B. (San Jose CA), Combined semiconductor device and printed circuit board assembly.
    상세보기
  4. Butt Sheldon H. (Godfrey IL), Composites of glass-ceramic to metal seals and method of making the same.
    상세보기
  5. Burgyan ; Stephan J., Composites of glass-ceramic-to-metal, seals and method of making same.
    상세보기
  6. Spinelli, Thomas S.; Manns, William G.; Weirauch, Donald F., Electronic circuit interconnection system.
    상세보기
  7. Sherman Charles J. (Westminster CO), Electronic device packaging arrangement.
    상세보기
  8. Popplewell James M. (Guilford CT), Glass or ceramic-to-metal composites or seals involving iron base alloys.
    상세보기
  9. Hascoe ; Norman, Hermetically sealed container for semiconductor and other electronic device s.
    상세보기
  10. Cossutta ; Giuseppe ; Cellai ; Marino, Molded body incorporating heat dissipator.
    상세보기
  11. Barnes Norman S. (Whitesboro NY) Mogle Rodman A. (Clinton NY), Molybdenum substrate thick film circuit.
    상세보기
  12. Takami Akio (Nagoya JPX) Kondo Kazuo (Nagoya JPX) Tanaka Kazutoshi (Nagoya JPX), Seal structure of ceramics and low expansion metallic material.
    상세보기
  13. Hutchison Robert V. (Oceanside CA), Semiconductor device package having lead frame structure with integral spring contacts.
    상세보기
  14. Narita Kazutoyo (Hitachi JA) Sakaue Tadashi (Hitachi JA) Niino Yuzi (Hitachi JA), Semiconductor device with composite metal heat-radiating plate onto which semiconductor element is soldered.
    상세보기
  15. Schneider Stanley (Newport Beach CA), Solid state relay having U-shaped conductive heat sink frame.
    상세보기
  16. Lifshin, Eric; Cargioli, Joseph D.; Schroder, Stephen J.; Wong, Joe, Transfer lamination of copper thin sheets and films, method and product.
    상세보기

이 특허를 인용한 특허 (91) 인용/피인용 타임라인 분석

  1. Rathburn, James, Area array semiconductor device package interconnect structure with optional package-to-package or flexible circuit to package connection.
    상세보기
  2. Rathburn, James, Bumped semiconductor wafer or die level electrical interconnect.
    상세보기
  3. Rathburn, James, Compliant conductive nano-particle electrical interconnect.
    상세보기
  4. Rathburn, James, Compliant conductive nano-particle electrical interconnect.
    상세보기
  5. Rathburn, James, Compliant core peripheral lead semiconductor socket.
    상세보기
  6. Rathburn, James, Compliant core peripheral lead semiconductor test socket.
    상세보기
  7. Rathburn, James, Compliant printed circuit area array semiconductor device package.
    상세보기
  8. Rathburn, James, Compliant printed circuit semiconductor package.
    상세보기
  9. Rathburn, James, Compliant printed circuit semiconductor package.
    상세보기
  10. Rathburn, James, Compliant printed circuit semiconductor tester interface.
    상세보기
  11. Rathburn, James, Compliant printed circuit socket diagnostic tool.
    상세보기
  12. Rathburn, James, Compliant printed circuit wafer level semiconductor package.
    상세보기
  13. Rathburn, James, Compliant printed circuit wafer probe diagnostic tool.
    상세보기
  14. Rathburn, James, Compliant printed flexible circuit.
    상세보기
  15. Rathburn, James, Compliant wafer level probe assembly.
    상세보기
  16. Rathburn, James, Composite polymer-metal electrical contacts.
    상세보기
  17. Akram, Salman, Copper interconnect.
    상세보기
  18. Akram,Salman, Copper interconnect.
    상세보기
  19. Akram,Salman, Copper interconnect.
    상세보기
  20. Akram,Salman, Copper interconnect for semiconductor device.
    상세보기
  21. Rathburn, James, Copper pillar full metal via electrical circuit structure.
    상세보기
  22. Rathburn, Jim, Copper pillar full metal via electrical circuit structure.
    상세보기
  23. Rathburn, James, Direct metalization of electrical circuit structures.
    상세보기
  24. Hoffman Paul R. ; Popplewell James M. ; Braden Jeffrey S., Edge connectable metal package.
    상세보기
  25. Rathburn, James, Electrical connector insulator housing.
    상세보기
  26. Rathburn, James, Electrical interconnect IC device socket.
    상세보기
  27. Rathburn, James, Electrical interconnect IC device socket.
    상세보기
  28. Temple Victor A. K., Flat power pack.
    상세보기
  29. Smith,Brian; Deju,Hector; Burri,Scott; Crider,Larry E.; Kreuzpaintner,Joseph; Jandzio,Gregory M.; Whybrew,Walter M., Flexible appliance and related method for orthogonal, non-planar interconnections.
    상세보기
  30. Ferguson, John Thomas, Focused LED headlamp with iris assembly.
    상세보기
  31. Rathburn, James, Fusion bonded liquid crystal polymer circuit structure.
    상세보기
  32. Xie,Hong; Frutschy,Kristopher; Banerjee,Koushik; Sathe,Ajit, Heat spreader and stiffener having a stiffener extension.
    상세보기
  33. Stephen Nicholas Siu, Heatsink retainer.
    상세보기
  34. Farnworth Warren M. ; Akram Salman ; Wood Alan G., Hermetic chip and method of manufacture.
    상세보기
  35. Farnworth Warren M. ; Akram Salman ; Wood Alan G., Hermetic chip and method of manufacture.
    상세보기
  36. Farnworth Warren M. ; Akram Salman ; Wood Alan G., Hermetic chip and method of manufacture.
    상세보기
  37. Farnworth, Warren M.; Akram, Salman; Wood, Alan G., Hermetic chip and method of manufacture.
    상세보기
  38. Farnworth, Warren M.; Akram, Salman; Wood, Alan G., Hermetic chip and method of manufacture.
    상세보기
  39. Farnworth, Warren M.; Akram, Salman; Wood, Alan G., Hermetic chip in wafer form.
    상세보기
  40. Farnworth Warren M., Hermetically sealed chip scale packages formed by wafer level fabrication and assembly.
    상세보기
  41. Rathburn, James, High performance electrical circuit structure.
    상세보기
  42. Rathburn, James, High performance surface mount electrical interconnect.
    상세보기
  43. Rathburn, James, High performance surface mount electrical interconnect.
    상세보기
  44. Rathburn, James, High performance surface mount electrical interconnect.
    상세보기
  45. Rathburn, James, High performance surface mount electrical interconnect with external biased normal force loading.
    상세보기
  46. Rathburn, James, High speed circuit assembly with integral terminal and mating bias loading electrical connector assembly.
    상세보기
  47. Rathburn, James, Hybrid printed circuit assembly with low density main core and embedded high density circuit regions.
    상세보기
  48. Rathburn, James J., Low profile electrical interconnect with fusion bonded contact retention and solder wick reduction.
    상세보기
  49. Beane Alan F. (Gilford NH) Beane Glenn L. (Plymouth NH), Manufacturing particles and articles having engineered properties.
    상세보기
  50. Beane Alan F. ; Beane Glenn L., Manufacturing particles and articles having engineered properties.
    상세보기
  51. Beane Alan F. ; Beane Glenn L., Manufacturing particles and articles having engineered properties.
    상세보기
  52. Rathburn, James J., Mechanical contact retention within an electrical connector.
    상세보기
  53. Guzek, John; Wood, Dustin, Metal core integrated circuit package with electrically isolated regions and associated methods.
    상세보기
  54. Tsukaguchi, Nobuyoshi; Kimura, Masami, Metal/ceramic circuit board.
    상세보기
  55. Rathburn, James, Metalized pad to electrical contact interface.
    상세보기
  56. Akram, Salman, Method and semiconductor device having copper interconnect for bonding.
    상세보기
  57. Tower Steven A. ; Mravic Brian, Method for making a ceramic to metal hermetic seal.
    상세보기
  58. Rathburn, James, Method of forming a semiconductor socket.
    상세보기
  59. Akram, Salman, Method of improving copper interconnects of semiconductor devices for bonding.
    상세보기
  60. Akram, Salman, Method of improving copper interconnects of semiconductor devices for bonding.
    상세보기
  61. Akram,Salman, Method of improving copper interconnects of semiconductor devices for bonding.
    상세보기
  62. Rathburn, James, Method of making a compliant printed circuit peripheral lead semiconductor package.
    상세보기
  63. Rathburn, James, Method of making a compliant printed circuit peripheral lead semiconductor test socket.
    상세보기
  64. Rathburn, James J., Method of making an electrical connector having electrodeposited terminals.
    상세보기
  65. Rathburn, Jim, Method of making an electronic interconnect.
    상세보기
  66. Tandy,William D.; Street,Bret K., Methods for marking a bare semiconductor die including applying a tape having energy-markable properties.
    상세보기
  67. Tandy,William D.; Street,Bret K., Methods for marking a packaged semiconductor die including applying tape and subsequently marking the tape.
    상세보기
  68. Farnworth, Warren M., Methods of wafer level fabrication and assembly of chip scale packages.
    상세보기
  69. Farnworth, Warren M., Methods of wafer level fabrication and assembly of chip scale packages.
    상세보기
  70. Tower Steven A. ; Mravic Brian, Optical component package with a hermetic seal.
    상세보기
  71. Harris James M. (Rte. 4 ; Box 240 Terrell TX 75160) Kiba Brigitte U. (3801 E. 14th St. #401 Plano TX 75074) Click ; Jr. Porter B. (612 Mt. Vernon Pl. Garland TX 75043), Package for a high frequency semiconductor device and methods for fabricating and connecting the same to an external cir.
    상세보기
  72. Frutschy,Kristopher; Chung,Chee Yee; Sankman,Bob, Package stiffener.
    상세보기
  73. Rathburn, James, Performance enhanced semiconductor socket.
    상세보기
  74. Silverman, Lawrence H., Pocket mounted chip having microstrip line.
    상세보기
  75. Rathburn, James, Resilient conductive electrical interconnect.
    상세보기
  76. Rathburn, James, Selective metalization of electrical connector or socket housing.
    상세보기
  77. Rathburn, Jim, Selective metalization of electrical connector or socket housing.
    상세보기
  78. Akram, Salman, Semiconductor device having copper interconnect for bonding.
    상세보기
  79. Rathburn, James, Semiconductor device package adapter.
    상세보기
  80. Rathburn, James, Semiconductor die terminal.
    상세보기
  81. Rathburn, James, Semiconductor socket with direct selective metalization.
    상세보기
  82. Rathburn, James, Simulated wirebond semiconductor package.
    상세보기
  83. Rathburn, James, Singulated semiconductor device separable electrical interconnect.
    상세보기
  84. Farnworth, Warren M., Stereolithographic methods for fabricating hermetic semiconductor device packages and semiconductor devices including stereolithographically fabricated hermetic packages.
    상세보기
  85. Farnworth, Warren M., Stereolithographic methods for fabricating hermetic semiconductor device packages and semiconductor devices including stereolithographically fabricated hermetic packages.
    상세보기
  86. Farnworth, Warren M., Stereolithographic methods for fabricating hermetic semiconductor device packages and semiconductor devices including stereolithographically fabricated hermetic packages.
    상세보기
  87. Weingand Christopher Dirk (23 A Holton St. Woburn MA 01801-5232), Surface mount package with heat transfer feature.
    상세보기
  88. Connell, Michael E.; Jiang, Tongbi, Wafer back side coating to balance stress from passivation layer on front of wafer and be used as die attach adhesive.
    상세보기
  89. Connell,Michael E.; Jiang,Tongbi, Wafer back side coating to balance stress from passivation layer on front of wafer and be used as die attach adhesive.
    상세보기
  90. Farnworth Warren M., Wafer level fabrication and assembly of chip scale packages.
    상세보기
  91. Farnworth Warren M., Wafer level fabrication and assembly of chip scale packages.
    상세보기

활용도 분석정보

상세보기
다운로드
내보내기

활용도 Top5 특허

해당 특허가 속한 카테고리에서 활용도가 높은 상위 5개 콘텐츠를 보여줍니다.
더보기 버튼을 클릭하시면 더 많은 관련자료를 살펴볼 수 있습니다.

관련 콘텐츠

저작권 관리 안내
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로