이 특허를 인용한 특허 (34)

1. Dimeo, Jr., Frank; Chen, Philip S. H.; Neuner, Jeffrey W.; Welch, James; Stawasz, Michele; Baum, Thomas H.; King, Mackenzie E.; Chen, Ing-Shin; Roeder, Jeffrey F., Apparatus and process for sensing fluoro species in semiconductor processing systems.

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2. Dimeo, Jr.,Frank; Chen,Philip S. H.; Neuner,Jeffrey W.; Welch,James; Stawacz,Michele; Baum,Thomas H.; King,Mackenzie E.; Chen,Ing Shin; Roeder,Jeffrey F., Apparatus and process for sensing fluoro species in semiconductor processing systems.

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3. Dimeo, Jr.,Frank; Chen,Philip S. H.; Neuner,Jeffrey W.; Welch,James; Stawasz,Michele; Baum,Thomas H.; King,Mackenzie E.; Chen,Ing Shin; Roeder,Jeffrey F., Apparatus and process for sensing fluoro species in semiconductor processing systems.

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4. Mahulikar Deepak ; Hoffman Paul R. ; Braden Jeffrey S., Ball grid array electronic package.

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5. Vatanparast, Ramin; Aarras, Mikko; Dunford, Steven O.; Fujii, Takaharu; Lainonen, Juhani; Nousiainen, Jaakko; Rantala, Jukka I.; Tanskanen, Pia; Yamamoto, Tetsuya, Composite layer for an electronic device.

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6. Sulfridge, Marc, Conductive interconnect structures and formation methods using supercritical fluids.

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7. Sulfridge, Marc, Conductive interconnect structures and formation methods using supercritical fluids.

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8. Sulfridge, Marc, Conductive interconnect structures and formation methods using supercritical fluids.

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9. Lim, Way Chet, Electronic device housings with holes.

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10. Whitton, David, Integrated electrical shield in a heat sink.

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11. Boon, Suan Jeung; Chia, Yong Poo; Eng, Meow Koon, Interconnects for packaged semiconductor devices and methods for manufacturing such devices.

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12. Boon, Suan Jeung; Chia, Yong Poo; Eng, Meow Koon, Interconnects for packaged semiconductor devices and methods for manufacturing such devices.

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13. Suan Jeung, Boon; Yong Poo, Chia; Meow Koon, Eng, Interconnects for packaged semiconductor devices and methods for manufacturing such devices.

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14. Celaya,Phillip C.; Donley,James S.; St. Germain,Stephen C., Lead-free integrated circuit package structure.

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15. Morris,Thomas M., Light emitting assembly with heat dissipating support.

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16. Mahulikar Deepak (Madison CT) Hoffman Paul R. (Modesto CA) Braden Jeffrey S. (Livermore CA), Metal ball grid array package with improved thermal conductivity.

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17. Vatanparast, Ramin; Aarras, Mikko; Dunford, Steven O.; Fujii, Takaharu; Lainonen, Juhani; Nousiainen, Jaakko; Rantala, Jukka I.; Tanskanen, Pia; Yamamoto, Tetsuya, Method for manufacturing a composite layer for an electronic device.

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18. Knodler Dieter,DEX, Method for manufacturing electrically conductive lead-throughs in metallized plastic housings.

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19. Celaya, Phillip C.; Donley, James S.; St. Germain, Stephen C., Method of making a lead-free integrated circuit package.

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20. Lim, Chang Hyun; Kang, Jung Eun; Park, Heung Soo; Choi, Seog Moon; Kim, Kwang Soo; Chae, Joon Seok; Park, Sung Keun, Method of manufacturing a hybrid heat-radiating substrate.

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21. Goto Masao (Yokohama JPX) Ikemizu Morihiko (Kawasaki JPX), Method of manufacturing a thin semiconductor package having many pins and likely to dissipate heat.

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22. Chong, Chin Hui; Lee, Choon Kuan, Method of manufacturing an interposer.

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23. Oda, Takuya, Method of manufacturing electronic component device.

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24. Sulfridge, Marc, Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods.

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25. Sulfridge, Marc, Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods.

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26. Sulfridge, Marc, Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods.

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27. Fogel Keith Edward ; Hedrick Jeffrey Curtis ; Lewis David Andrew ; Simonyi Eva E. ; Viehbeck Alfred ; Whitehair Stanley Joseph, Methods of fabrication of coaxial vias and magnetic devices.

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28. Hiatt, William M.; Dando, Ross S., Microfeature workpieces and methods for forming interconnects in microfeature workpieces.

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29. Tuttle, Mark E., Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods.

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30. Tuttle, Mark E., Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods.

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31. Wen-chou Vincent Wang ; Thomas J. Massingill ; Yasuhito Takahashi ; Lei Zhang, Modules with pins and methods for making modules with pins.

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32. Mahulikar Deepak (Madison CT) Tyler Derek E. (Cheshire CT) Braden Jeffrey S. (Livermore CA) Popplewell James M. (Guilford CT), Molded plastic semiconductor package including heat spreader.

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33. Dimeo, Jr.,Frank; Chen,Philip S. H.; Chen,Ing Shin; Neuner,Jeffrey W.; Welch,James, Nickel-coated free-standing silicon carbide structure for sensing fluoro or halogen species in semiconductor processing systems, and processes of making and using same.

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34. Kang,Suk Chae; Kang,Sa Yoon; Kim,Dong Han; Lee,Si Hoon, Semiconductor package and method for its manufacture.

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