이 특허를 인용한 특허 (52)

1. Hong Merit Y., Apparatus and method of orienting asymmetrical semiconductor devices in a circuit.

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2. Duane Michael ; Gardner Mark I., Asymmetrical MOSFET with gate pattern after source/drain formation.

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3. Kadosh Daniel ; Gardner Mark I., Asymmetrical N-channel and P-channel devices.

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4. Kadosh, Daniel; Gardner, Mark I., Asymmetrical N-channel and P-channel devices.

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5. Kadosh Daniel ; Hause Fred N. ; Cheek Jon D., Asymmetrical P-channel transistor having a boron migration barrier and a selectively formed sidewall spacer.

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6. Kadosh Daniel ; Gardner Mark I., Asymmetrical p-channel transistor formed by nitrided oxide and large tilt angle LDD implant.

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7. Fulford H. Jim ; Gardner Mark I., Asymmetrical transistor having a gate dielectric which is substantially resistant to hot carrier injection.

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8. Kadosh Daniel ; Gardner Mark I. ; Duane Michael ; Cheek Jon D. ; Hause Fred N. ; Dawson Robert ; Moore Brad T., Asymmetrical transistor structure.

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9. Kadosh Daniel ; Gardner Mark I. ; Dawson Robert, Asymmetrical transistor with lightly and heavily doped drain regions and ultra-heavily doped source region.

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10. Gardner Mark I. ; Fulford ; Jr. H. Jim ; Wristers Derick J., Asymmetrical transistor with lightly doped drain region, heavily doped source and drain regions, and ultra-heavily dope.

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11. Gardner Mark I. ; Fulford ; Jr. H. Jim, Detached drain MOSFET.

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12. Mark I. Gardner ; H. Jim Fulford, Jr., Detached drain MOSFET.

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13. Eng, Yi Chuen, Field effect transistor and method for fabricating field effect transistor.

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14. Gardner Mark I. ; Gilmer Mark C., High density mosfet fabrication method with integrated device scaling.

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15. Gardner Mark I. ; Kadosh Daniel ; Hause Fred, High performance asymmetrical MOSFET structure and method of making the same.

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16. Kitamura Tadao,JPX ; Shinohara Hisaji,JPX, Insulating supporting structure for high-voltage apparatus including inorganic insulating layer formed on a surface of an organic insulating structure.

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17. Fulford ; Jr. H. Jim ; Gardner Mark I. ; Wristers Derick J., Integrated circuit gate conductor having a gate dielectric which is substantially resistant to hot carrier effects.

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18. Cheek Jon D. ; Wristers Derick J. ; Toprac Anthony J., Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant.

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19. Cheek Jon D. ; Wristers Derick J. ; Toprac Anthony J., Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant.

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20. Gardner Mark I. ; Fulford ; Jr. H. Jim ; Wristers Derick J., MOSFET device with an amorphized source.

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21. Gardner Mark I. ; Fulford ; Jr. H. Jim ; Wristers Derick J., MOSFET device with an amorphized source and fabrication method thereof.

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22. Gardner Mark I. ; Hause Frederick N. ; Duane Michael P., Mask for asymmetrical transistor formation with paired transistors.

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23. Zhou Mei Sheng,SGX ; Pradeep Yelehanka Ramachandramurthy,SGX ; Xu Dajiang,SGX, Method for a lightly doped drain structure.

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24. Rha Sa Kyun,KRX ; Cheon Young Il,KRX, Method for fabricating thin film transistors.

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25. Gardner Mark I. ; Wristers Derick J. ; Fulford ; Jr. H. Jim, Method for fabrication of a non-symmetrical transistor with sequentially formed gate electrode sidewalls.

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26. Kadosh Daniel ; Gardner Mark I., Method for forming asymmetrical p-channel transistor having nitrided oxide patterned to selectively form a sidewall spac.

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27. Yang Ching-Nan (Hsinchu TWX), Method for forming blanket planarization of the multilevel interconnection.

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28. Gardner Mark I. ; Wristers Derick J. ; Fulford ; Jr. H. Jim, Method for making asymmetrical N-channel and symmetrical P-channel devices.

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29. Yamazaki Yasushi (Tokyo JPX), Method for manufacturing asymmetrical LDD type MIS device.

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30. Selcuk Asim, Method of asymmetrically doping a region beneath a gate.

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31. Ling Zicheng Gary ; Chiang James, Method of fabricating ultra shallow junction CMOS transistors with nitride disposable spacer.

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32. Ling, Zicheng Gary; Chiang, James, Method of fabricating ultra shallow junction CMOS transistors with nitride disposable spacer.

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33. Gardner Mark ; Wristers Derick J., Method of forming a semiconductor device having narrow gate electrode.

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34. Lin Ming-Ren ; Fang Peng ; Wollesen Donald L., Method of forming asymmetrically doped source/drain regions.

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35. Lin Ming-Ren ; Fang Peng ; Wollesen Donald L., Method of forming asymmetrically doped source/drain regions.

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36. Gardner Mark I. ; Wristers Derick J. ; Fulford ; Jr. H. Jim, Method of making N-channel and P-channel devices using two tube anneals and two rapid thermal anneals.

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37. Gardner Mark I. ; Duane Michael ; Kadosh Daniel, Method of making an IGFET with a non-uniform lateral doping profile in the channel region.

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38. Gardner Mark I. ; Kadosh Daniel ; Duane Michael, Method of making an IGFET with a selectively doped gate in combination with a protected resistor.

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39. Gardner Mark I. ; Kadosh Daniel, Method of making an asymmetrical IGFET and providing a field dielectric between active regions of a semiconductor substr.

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40. Kadosh Daniel ; Gardner Mark I. ; Dawson Robert, Method of making an asymmetrical transistor with lightly and heavily doped drain regions and ultra-heavily doped source.

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41. Kadosh Daniel (Austin TX) Gardner Mark I. (Cedar Creek TX), Method of making asymmetrical N-channel and P-channel devices.

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42. Kadosh Daniel ; Gardner Mark I. ; Dawson Robert, Method of making asymmetrical transistor with lightly and heavily doped drain regions and ultra-heavily doped source reg.

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43. Draper Donald A., Method of making transistor with selectively doped channel region for threshold voltage control.

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44. Park Heemyong ; Ilderem Vida ; Davies Robert B., Method of manufacturing an insulated gate semiconductor device having a spacer extension.

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45. Gardner Mark I. ; Fulford ; Jr. H. Jim, Process of fabricating transistors having source and drain regions laterally displaced from the transistors gate.

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46. Chou,Anthony I.; Furukawa,Toshiharu; Holmes,Steven J., Selective post-doping of gate structures by means of selective oxide growth.

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47. Fulford ; Jr. H. Jim ; Gardner Mark I., Selective spacer formation for optimized silicon area reduction.

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48. Fulford ; Jr. H. Jim ; Gardner Mark I., Selective spacer formation for optimized silicon area reduction.

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49. Rha Sa Kyun,KRX ; Cheon Young Il,KRX, Thin film transistor and method for fabricating thereof.

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50. Gardner Mark I. ; Fulford ; Jr. H. Jim, Ultra-short transistor fabrication scheme for enhanced reliability.

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51. Gardner Mark I. ; Fulford ; Jr. H. Jim, Ultra-short transistor fabrication scheme for enhanced reliability.

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52. Lin Jengping (Tayuan Village TWX) Chien Sun-Chieh (Hsin-chu TWX), Use of oxide spacers formed by liquid phase deposition.

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