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VDMOS transistor and manufacturing method therefor 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/68
출원번호 US-0330567 (1994-10-28)
발명자 / 주소
  • Yang Sheng-Hsing (Hsinchu TWX)
출원인 / 주소
  • United Microelectronics Corp. (Hsin-Chu TWX 03)
인용정보 피인용 횟수 : 122  인용 특허 : 0

초록 ▼

A VDMOS transistor having a reduced drain/source resistance without a corresponding decrease in breakdown voltage and a manufacturing method therefor. Such a VDMOS transistor is created by gradually increasing the doping density of the transistor\s implanted regions, while simultaneously increasing

대표청구항 ▼

A VDMOS transistor on a semiconductor substrate, comprising: a drain electrode region of a first conductivity type in said substrate, said drain electrode region having a drain electrode region doping density (D+); an epitaxial layer of said first conductivity type formed on said drain electrode reg

이 특허를 인용한 특허 (122)

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