이 특허를 인용한 특허 (161)

1. Nallan Padmapani ; Kumar Ajay ; Chinn Jeffrey, Anisotropic silicon nitride etching for shallow trench isolation in an high density plasma system.

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2. Smith,David Walter; Brehm,William Albert; DiPrinzio,Steven John, Bidirectional singulation saw and method.

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3. Yeo, Yee-Chia; Hu, Chenming, Capacitor that includes high permittivity capacitor dielectric.

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4. Yeo, Yee-Chia; Hu, Chenming, Capacitor that includes high permittivity capacitor dielectric.

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5. Yeo, Yee-Chia; Hu, Chenming, Capacitor with enhanced performance and method of manufacture.

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6. Joachim Hans-Oliver ; Mandelman Jack A. ; Rengarajan Rajesh, Deep pivot mask for enhanced buried-channel PFET performance and reliability.

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7. Knoefler,Roman; Tilke,Armin, Direct channel stress.

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8. Fu, Ssu-I; Hung, Yu-Hsiang; Chen, Cheng-Guo; Chang, Chung-Fu; Lin, Chien-Ting, Epitaxial Process of forming stress inducing epitaxial layers in source and drain regions of PMOS and NMOS structures.

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9. Morikado,Mutsuo, Floating-body cell (FBC) semiconductor storage device having a buried electrode serving as gate electrode, and a surface electrode serving as plate electrode.

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10. Hyun Sook Shim KR, Impurity ion segregation precluding layer, fabrication method thereof, isolation structure for semiconductor device using the impurity ion segregation precluding layer and fabricating method thereof.

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11. Park, Tai-su; Park, Moon-han; Park, Kyung-won; Lee, Han-sin; Kim, Jung-yup; Hong, Chang-ki; Kang, Ho-kyu, Integrated circuit device isolation methods using high selectivity chemical-mechanical polishing.

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12. Joyner Keith A. ; Loewenstein Lee M., Isolation structure and method.

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13. Ko, Chih-Hsin; Yeo, Yee-Chia; Lee, Wen-Chin; Ge, Chung-Hu, Isolation structure for strained channel transistors.

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14. Fazan Pierre C. ; Roberts Martin C. ; Sandhu Gurtej S., Isolation structure of a shallow semiconductor device trench.

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15. Ko, Chih-Hsin; Yeo, Yee-Chia; Ge, Chung-Hu; Lee, Wen-Chin, Isolation structure with nitrogen-containing liner and methods of manufacture.

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16. Ahn, Yongchul; Wong, Kaichiu; Jayatilaka, Venuka, Isolation technology for submicron semiconductor devices.

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17. Smythe, III, John A.; Trivedi, Jigish D., Isolation trench.

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18. Trivedi,Jigish D.; Patraw,Robert D.; Beaman,Kevin L.; Smythe, III,John A., Liner for shallow trench isolation.

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19. Inoue,Kengo; Mori,Toshifumi; Nakamura,Ryou; Ohta,Hiroyuki; Saiki,Takashi, Manufacture of semiconductor device having STI and semiconductor device manufactured.

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20. Jack A. Mandelman ; Rama Divakaruni ; Herbert Ho ; Giuseppe La Rosa ; Yujun Li ; Jochen Beintner ; Radhika Srinivasan, Method and device for array threshold voltage control by trapped charge in trench isolation.

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21. Kim, Chul-Sung; Choi, Si-Young; Park, Jung-Woo; Ryu, Jong-Ryol; Lee, Byeong-Chan, Method and device for forming an STI type isolation in a semiconductor device.

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22. Kim, Chul-Sung; Choi, Si-Young; Park, Jung-Woo; Ryu, Jong-Ryol; Lee, Byeong-Chan, Method and device for forming an STI type isolation in a semiconductor device.

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23. Kim, Chul-Sung; Choi, Si-Young; Park, Jung-Woo; Ryu, Jong-Ryol; Lee, Byeong-Chan, Method and device for forming an STI type isolation in a semiconductor device.

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24. Ramkumar, Krishnaswamy; Bamnolker, Hanna, Method for controlling the oxidation of implanted silicon.

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25. Hung, Wen-Han; Chen, Tsai-Fu; Lo, Ta-Kang; Cheng, Tzyy-Ming, Method for fabricating semiconductor device.

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26. Lin Xi-Wei ; Lee Henry ; Harvey Ian R., Method for fabrication of a semiconductor device.

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27. Lin Xi-Wei ; Lee Henry ; Harvey Ian R., Method for fabrication of a semiconductor device.

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28. Gonzalez, Fernando; Chapek, David L.; Thakur, Randhir P. S., Method for forming a self-aligned isolation structure utilizing sidewall spacers as an etch mask and remaining as a portion of the isolation structure.

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29. Park Tai-Su,KRX ; Lee Han-Sin,KRX ; Shin Yu-Gyun,KRX, Method for forming a trench isolation structure in an integrated circuit.

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30. Kim Chang-gyu,KRX ; Chung Woo-in,KRX, Method for forming insulating films in semiconductor devices.

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31. Joo, Joon-Yong, Method for forming isolation trench.

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32. Tien Yu-Chung,TWX, Method for forming shallow trench isolations.

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33. Jong-Seung Yi KR; Tae Wook Seo KR; Jin-Ho Jeon KR, Method for forming trench isolation regions.

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34. Hsu, Ching-Pin; Lin, Yi-Po; Liao, Jiunn-Hsiung; Chen, Chieh-Te; Chang, Feng-Yi; Tsai, Shang-Yuan; Chen, Li-Chiang, Method for forming void-free dielectric layer.

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35. Nakamori, Toshiya; Kujirai, Hiroshi, Method for manufacturing semiconductor device.

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36. Maniar Papu D. (Austin TX) Fiordalice Robert W. (Austin TX), Method for providing trench isolation.

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37. Maniar Papu D. (Austin TX) Fiordalice Robert W. (Austin TX), Method for providing trench isolation and borderless contact.

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38. Beekman, Knut; Patel, Jashu, Method for treating silicon-containing polymer layers with plasma or electromagnetic radiation.

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39. Brosnihan, Timothy J.; Bustillo, James; Clark, William A., Method of fabricating a microfabricated high aspect ratio device with electrical isolation.

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40. Yew Tri-Rung,TWX ; Lur Water,TWX ; Sun Shih-Wei,TWX, Method of fabricating a shallow-trench isolation structure in integrated circuit.

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41. Jenq Jason J. S.,TWX, Method of fabricating shallow trench isolation.

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42. Wu Kun-Lin,TWX ; Lu Horng-Bor,TWX, Method of fabricating shallow trench isolation.

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43. Vassiliev Vladislav,SGX ; Peidous Igor,SGX, Method of filling shallow trenches.

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44. Yeo,Yee Chia; Hu,Chenming, Method of forming a capacitor that includes forming a bottom electrode in a strained silicon layer.

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45. Iguchi, Souichirou; Watanabe, Takayuki; Kiyono, Junji, Method of forming a trench isolation structure resistant to hot phosphoric acid by extending trench liner to shoulder portions.

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46. Smythe, III,John A.; Budge,William, Method of forming an isolation structure that includes forming a silicon layer at a base of the recess.

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47. Chien, Chin-Cheng; Wu, Chun-Yuan; Liu, Chih-Chien; Lin, Chin-Fu; Tsai, Teng-Chun, Method of forming semiconductor device.

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48. Pei-Ren Jeng TW, Method of forming shallow trench isolation.

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49. Wang Larry Yu, Method of forming trench isolation with high integrity, ultra thin gate oxide.

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50. Gardner, Mark I.; Gilmer, Mark C.; Paiz, Robert, Method of making enhanced trench oxide with low temperature nitrogen integration.

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51. Takahashi Minoru,JPX ; Matsuoka Fumitomo,JPX ; Ishimaru Kazunari,JPX, Method of manufacturing a gap filling for shallow trench isolation.

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52. Kanamitsu, Kenji; Watanabe, Kouzou; Suzuki, Norio; Ishitsuka, Norio, Method of manufacturing a semiconductor integrated circuit device having a trench.

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53. Kanamitsu, Kenji; Watanabe, Kouzou; Suzuki, Norio; Ishitsuka, Norio, Method of manufacturing a semiconductor integrated circuit device having a trench.

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54. Yeo,Yee Chia; Hu,Chenming, Method of manufacturing an integrated circuit including capacitor with high permittivity capacitor dielectric.

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55. Tsai Meng-Jin,TWX, Method of manufacturing shallow trench isolation structure.

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56. Miner Gary E. ; Xing Guangcai ; Lopes David R. ; Kuppurao Sathees, Method of oxidizing a substrate in the presence of nitride and oxynitride films.

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57. Huang, Jui Tsen, Method of relieving wafer stress.

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58. Fazan Pierre C. ; Roberts Martin C. ; Sandhu Gurtej S., Method of trench isolation using spacers to form isolation trenches with protected corners.

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59. Qian Gang,SGX ; Gan Chock Hing,SGX ; Chan Lap Hung ; Tan Poh Suan,SGX, Method to avoid dishing in forming trenches for shallow trench isolation.

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60. Lin, Yai-Fen; Lin, Chang Song; Hsieh, Chia-Ta; Sung, Hung-Cheng; Yeh, Juang-Ke, Method to fabricate a non-smiling effect structure in split-gate flash with self-aligned isolation.

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61. Yai-Fen Lin TW; Chang-Song Lin TW; Chia-Ta Hsieh TW; Hung-Cheng Sung TW; Juang-Ke Yeh TW, Method to fabricate a non-smiling effect structure in split-gate flash with self-aligned isolation.

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62. Kong-Beng Thei TW; Kuei-Ying Lee TW; Dun-Nian Yaung TW; Shou-Gwo Wuu TW, Method to reduce defects in shallow trench isolations by post liner anneal.

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63. Trivedi, Jigish D.; Patraw, Robert D.; Beaman, Kevin L.; Smythe, III, John A., Methods for forming shallow trench isolation.

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64. Stapelmann, Chris; Tilke, Armin, Methods of fabricating isolation regions of semiconductor devices and structures thereof.

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65. Tilke, Armin; Culmsee, Marcus; Stapelmann, Chris; Hong, Bee Kim; Hampp, Roland, Methods of fabricating isolation regions of semiconductor devices and structures thereof.

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66. Tilke, Armin; Culmsee, Marcus; Stapelmann, Chris; Hong, Bee Kim; Hampp, Roland, Methods of fabricating isolation regions of semiconductor devices and structures thereof.

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67. Juengling, Werner; Lane, Richard, Methods of forming an integrated circuit with self-aligned trench formation.

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68. Hwang Ki-Hyun,KRX ; Nam Seok-Woo,KRX, Methods of forming isolation trenches including damaging a trench isolation mask.

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69. Sharan, Sujit; Sandhu, Gurtej S., Methods of forming silicon dioxide layers and methods of forming trench isolation regions.

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70. Sharan, Sujit; Sandhu, Gurtej S., Methods of forming silicon dioxide layers, and methods of forming trench isolation regions.

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71. Sharan,Sujit; Sandhu,Gurtej S., Methods of forming silicon dioxide layers, and methods of forming trench isolation regions.

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72. Sharan,Sujit; Sandhu,Gurtej S., Methods of forming silicon dioxide layers, and methods of forming trench isolation regions.

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73. Sung-eui Kim KR; Keum-joo Lee KR; In-seak Hwang KR; Young-sun Koh KR; Dong-ho Ahn KR; Moon-han Park KR; Tai-su Park KR, Methods of forming trench isolation regions having recess-inhibiting layers therein that protect against overetching.

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74. Hong Soo-Jin,KRX ; Yu Yung-Seob,KRX ; Koo Bon-Young,KRX ; Kim Byung-Ki,KRX ; Shin Seung-Mok,KRX, Methods of forming trench isolation regions having stress-reducing nitride layers therein.

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75. Oh Yong-Chul,KRX, Methods of forming trench isolation regions using preferred stress relieving layers and techniques to inhibit the occurrence of voids.

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76. Bronner Gary Bela ; Gambino Jeffrey Peter ; Nesbit Larry A., Methods to prevent divot formation in shallow trench isolation areas.

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77. Gardner Mark I. ; Hause Fred N. ; Chang Kuang-Yeh, Nitrogenated trench liner for improved shallow trench isolation.

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78. Ramkumar, Krishnaswamy; Wong, Kaichiu; Jayatilaka, Venuka, Process for reducing leakage in an integrated circuit with shallow trench isolated active areas.

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79. Chang Jung-Ho,TWX ; Chen Hsi-Chuan,TWX ; Lin Dahcheng,TWX, Process to reduce defect formation occurring during shallow trench isolation formation.

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80. Rengarajan Rajesh ; Jaiprakash Venkatachalam C., Recessed shallow trench isolation structure nitride liner and method for making same.

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81. Rengarajan, Rajesh; Jaiprakash, Venkatachalam C., Recessed shallow trench isolation structure nitride liner and method for making same.

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82. Yeo,Yee Chia; Hu,Chenming, Resistor with reduced leakage.

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83. Cheng, Kangguo; Haran, Balasubramanian S.; Ponoth, Shom, SOI device with embedded liner in box layer to limit STI recess.

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84. Lin Tony,TWX ; Yeh Wen-Kuan,TWX ; Huang Heng-Sheng,TWX, STI process for eliminating kink effect.

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85. Chen,Ming Te; Wu,Yi Ching; Huang,Chien Tung, STI process for eliminating silicon nitride liner induced defects.

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86. Juengling, Werner; Lane, Richard, Self-aligned semiconductor trench structures.

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87. Werner, Juengling; Lane, Richard, Self-aligned semiconductor trench structures.

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88. Juengling, Werner; Lane, Richard, Self-aligned trench formation.

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89. Wu, Chun-Yuan; Liu, Chih-Chien, Semiconductor device.

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90. Chou, Ling-Chun; Wang, I-Chang; Hung, Ching-Wen, Semiconductor device and manufacturing method thereof.

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91. Kunikiyo Tatsuya,JPX, Semiconductor device and method of manufacturing the same.

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92. Ishitsuka Norio,JPX ; Miura Hideo,JPX ; Ikeda Shuji,JPX ; Suzuki Norio,JPX ; Matsuda Yasushi,JPX ; Yoshida Yasuko,JPX ; Yamamoto Hirohiko,JPX ; Kobayashi Masamichi,JPX ; Takamatsu Akira,JPX ; Shimizu, Semiconductor device and process for producing the same.

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93. Ishitsuka, Norio; Miura, Hideo; Ikeda, Shuji; Suzuki, Norio; Matsuda, Yasushi; Yoshida, Yasuko; Yamamoto, Hirohiko; Kobayashi, Masamichi; Takamatsu, Akira; Shimizu, Hirofumi; Fukuda, Kazushi; Horibe,, Semiconductor device and process for producing the same.

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94. Ishitsuka,Norio; Miura,Hideo; Ikeda,Shuji; Suzuki,Norio; Matsuda,Yasushi; Yoshida,Yasuko; Yamamoto,Hirohiko; Kobayashi,Masamichi; Takamatsu,Akira; Shimizu,Hirofumi; Fukuda,Kazushi; Horibe,Shinichi; Nozoe,Toshio, Semiconductor device and process for producing the same.

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95. Ishitsuka, Norio; Miura, Hideo; Ikeda, Shuji; Suzuki, Norio; Matsuda, Yasushi; Yoshida, Yasuko; Yamamoto, Hirohiko; Kobayashi, Masamichi; Takamatsu, Akira; Shimizu, Hirofumi; Fukuda, Kazushi; Horibe,, Semiconductor device and process for producing the sme.

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96. Knoefler, Roman; Tilke, Armin, Semiconductor device formed in a recrystallized layer.

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97. Ookura, Yoshiyuki, Semiconductor device having STI with nitride liner and UV light shielding film.

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98. Ookura, Yoshiyuki, Semiconductor device having STI with nitride liner and UV light shielding film.

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99. Gardner Mark I. ; Gilmer Mark C., Semiconductor device having a nitrogen bearing isolation region.

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100. Lee, Jae-Hwan; Kim, Sangsu; Yang, Changjae, Semiconductor device having fin-type field effect transistor and method of manufacturing the same.

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101. Joo-Wook Park KR, Semiconductor device having shallow trench isolation structure and manufacturing method thereof.

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102. Park, Joo-Wook, Semiconductor device having shallow trench isolation structure and manufacturing method thereof.

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103. Ohta, Hiroyuki; Iriyama, Yasunori, Semiconductor device with STI and its manufacture.

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104. Chang, Chung-Fu; Hung, Yu-Hsiang; Huang, Shin-Chuan; Liu, Chia-Jong; Wu, Yen-Liang; Chou, Pei-Yu, Semiconductor process.

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105. Tsai, Tzung-I; Lu, Shui-Yen, Semiconductor process.

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106. Tran, Luan C., Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry.

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107. Tran,Luan C., Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry.

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108. Tran,Luan C., Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry.

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109. Gardner Mark I. ; Kwong Dim-Lee ; Fulford ; Jr. H. Jim, Semiconductor topography employing a nitrogenated shallow trench isolation structure.

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110. Yeo, Yee-Chia; Yang, Fu-Liang; Hu, Chenming, Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors.

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111. Yeo,Yee Chia; Yang,Fu Liang; Hu,Chenming, Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors.

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112. Yeo, Yee-Chia; Chen, How-Yu; Huang, Chien-Chao; Lee, Wen-Chin; Yang, Fu-Liang; Hu, Chenming, Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors.

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113. Yeo,Yee Chia; Chen,How Yu; Huang,Chien Chao; Lee,Wen Chin; Yang,Fu Liang; Hu,Chenming, Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors.

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114. Liu, Yanxiang; van Meer, Johannes M.; Yang, Xiaodong; Eller, Manfred J., Shallow trench isolation.

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115. Peidous Igor V.,SGX, Shallow trench isolation of MOSFETS with reduced corner parasitic currents.

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116. Yu Chen-Hua,TWX ; Jang Syun-Ming,TWX, Shallow trench isolation process employing a BPSG trench fill.

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117. Yu Chen-Hua,TWX ; Jang Syun-Ming,TWX, Shallow trench isolation process for reduced for junction leakage.

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118. Doong, Kelvin Yih Yuh, Shallow trench isolation scheme for border-less contact process.

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119. Huang Kuo Ching,TWX ; Ying Tse-Liang,TWX ; Chiang Wen-Chuan,TWX ; Shih Cheng-Yeh,TWX, Shallow trench isolation technology to eliminate a kink effect.

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120. Benedict John Preston ; Dobuzinsky David Mark ; Flaitz Philip Lee ; Hammerl Erwin N.,DEX ; Ho Herbert ; Moseman James F. ; Palm Herbert,DEX ; Yoshida Seiko,JPX ; Takato Hiroshi, Shallow trench isolation with oxide-nitride/oxynitride liner.

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121. Benedict John Preston ; Dobuzinsky David Mark ; Flaitz Philip Lee ; Hammerl Erwin N.,DEX ; Ho Herbert ; Moseman James F. ; Palm Herbert,DEX ; Yoshida Seiko,JPX ; Takato Hiroshi, Shallow trench isolation with oxide-nitride/oxynitride liner.

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122. Chou, Ling-Chun; Wang, I-Chang; Hung, Ching-Wen, Spacer scheme for semiconductor device.

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123. Hou, Yung-Chin; Lu, Lee-Chung; Guo, Ta-Pen; Tien, Li-Chun; Li, Ping Chung; Tai, Chun-Hui; Chen, Shu-Min, Standard cell without OD space effect in Y-direction.

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124. Wang, Yen-Sen; Lin, Chung-Te; Cao, Min; Yang, Sheng-Jier, Strain bars in stressed layers of MOS devices.

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125. Ko,Chih Hsin; Yeo,Yee Chia; Lee,Wen Chin; Hu,Chenming, Strained channel complementary field-effect transistors.

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126. Ko,Chih Hsin; Yeo,Yee Chia; Lee,Wen Chin; Hu,Chenming, Strained channel complementary field-effect transistors and methods of manufacture.

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127. Ge, Chung-Hu; Wang, Chao-Hsuing; Huang, Chien-Chao; Lee, Wen-Chin; Hu, Chenming, Strained channel on insulator device.

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128. Ge,Chung Hu; Wang,Chao Hsiung; Huang,Chien Chao; Lee,Wen Chin; Hu,Chenming, Strained channel on insulator device.

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129. Yeo,Yee Chia; Ko,Chih Hsin; Lee,Wen Chin; Hu,Chenming, Strained channel transistor and methods of manufacture.

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130. Huang, Yi-Chun; Wang, Yen-Ping; Ko, Chih-Hsin, Strained channel transistor formation.

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131. Lindsay, Richard, Strained semiconductor device and method of making same.

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132. Lindsay, Richard, Strained semiconductor device and method of making same.

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133. Ge, Chung-Hu; Lee, Wen-Chin; Hu, Chenming, Strained silicon structure.

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134. Ge,Chung Hu; Lee,Wen Chin; Hu,Chenming, Strained silicon structure.

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135. Chuang, Harry; Thei, Kong-Beng; Guo, Wen-Huei; Liang, Mong Song, Strained transistor with optimized drive current and method of forming.

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136. Yeo, Yee-Chia; Ko, Chih-Hsin; Lee, Wen-Chin; Hu, Chenming, Strained-channel transistor and methods of manufacture.

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137. Ko, Chih-Hsin; Lee, Wen-Chin; Yeo, Yee-Chia; Lin, Chun-Chieh; Hu, Chenming, Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit.

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138. Ko,Chih Hsin; Lee,Wen Chin; Yeo,Yee Chia; Lin,Chun Chieh; Hu,Chenming, Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit.

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139. Jang Syun-Ming,TWX, Sub-atmospheric pressure thermal chemical vapor deposition (SACVD) trench isolation method with attenuated surface sensitivity.

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140. Syun-Ming Jang TW, Sub-atmospheric pressure thermal chemical vapor deposition (SACVD) trench isolation method with attenuated surface sensitivity.

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141. Smythe, III,John A.; Trivedi,Jigish D., Sub-micron space liner and densification process.

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142. Smythe, III, John A.; Trivedi, Jigish D., Sub-micron space liner and filler process.

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143. Tran,Luan C., Transistor assemblies.

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144. Tran,Luan C., Transistor assembly.

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145. Bernhardt, Henry; Stadtmüller, Michael; Storbeck, Olaf; Kainz, Stefan, Trench capacitor structure and process for applying a covering layer and a mask for trench etching processes in semiconductor substrates.

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146. Kawahara, Hideaki; Yang, Hong; Kocon, Christopher Boguslaw; Xiong, Yufei; Liu, Yunlong, Trench having thick dielectric selectively on bottom portion.

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147. Smythe, III,John A.; Budge,William, Trench insulation structures including an oxide liner and oxidation barrier.

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148. Smythe, III,John A.; Budge,William, Trench insulation structures including an oxide liner that is thinner along the walls of the trench than along the base.

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149. Hong Sug-hun,KRX, Trench isolated integrated circuits including voids.

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150. Hong Sug-hun,KRX, Trench isolation method.

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151. Song Jong-kook,KRX ; Kim Han-mil,KRX ; Ahn Dong-ho,KRX, Trench isolation method of semiconductor device.

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152. Hong,Sug hun, Trench isolation method with an epitaxially grown capping layer.

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153. Park Moon-han,KRX ; Hong Sug-hun,KRX ; Shin Yu-gyun,KRX, Trench isolation methods utilizing composite oxide films.

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154. Moon Peter K. ; Krick David T. ; Spurgin Kerry L., Trench isolation process using nitrogen preconditioning to reduce crystal defects.

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155. Moon Peter K. ; Krick David T. ; Spurgin Kerry L., Trench isolation process using nitrogen preconditioning to reduce crystal defects.

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156. Kim, Sung-eui; Lee, Keum-joo; Hwang, In-seak; Koh, Young-sun; Ahn, Dong-ho; Park, Moon-han; Park, Tai-su, Trench isolation regions having recess-inhibiting layers therein that protect against overetching.

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157. Tai-su Park KR; Moon-han Park KR; Kyung-won Park KR; Han-sin Lee KR, Trench isolation regions having trench liners with recessed ends.

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158. Fulford ; Jr. H. Jim ; Gardner Mark I. ; May Charles E., Trench isolation structure having a low K dielectric encapsulated by oxide.

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159. Gardner Mark I. ; Fulford ; Jr. H. Jim ; May Charles E., Trench isolation structure having a low K dielectric material isolated from a silicon-based substrate.

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160. Gardner Mark I. ; Fulford ; Jr. H. Jim ; May Charles E., Trench isolation structure partially bound between a pair of low K dielectric structures.

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161. Park Tai-su,KRX ; Park Moon-han,KRX ; Park Kyung-won,KRX ; Lee Han-sin,KRX, Trench isolation structure, semiconductor device having the same, and trench isolation method.

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