초록 ▼

An method is provided for fabricating a metal silicide upon a semiconductor topography. The method advantageously performs the anneal cycles at a substantially lower temperature. By employing a high pressure anneal chamber, temperature equilibrium is achieved across the semiconductor topography and

An method is provided for fabricating a metal silicide upon a semiconductor topography. The method advantageously performs the anneal cycles at a substantially lower temperature. By employing a high pressure anneal chamber, temperature equilibrium is achieved across the semiconductor topography and especially in small silicide formation areas. The higher pressure helps ensure thermal contact of heated, flowing gas across relatively small geometries in which silicide is to be formed. Substantial metal silicide formation can occur at the higher pressures even under relatively lower temperature conditions. The lower temperature process helps ensure that pre-existing implant regions remain at their initial position. The present metal silicide process and lower temperature anneal is therefore well suited to avoid impurity migration problems such as, for example, threshold skew, parasitic junction capacitance enhancement, and gate oxide degradation.

대표청구항 ▼

A method for fabricating a metal silicide region upon a semiconductor topography, comprising: providing a semiconductor substrate upon which a semiconductor topography is formed, said topography comprises a substrate dopant region and a polysilicon region configured across a portion of said topograp

A method for fabricating a metal silicide region upon a semiconductor topography, comprising: providing a semiconductor substrate upon which a semiconductor topography is formed, said topography comprises a substrate dopant region and a polysilicon region configured across a portion of said topography; depositing a metal layer upon said semiconductor topography to form a metal coated topography; placing said metal coated topography into an annealing chamber; annealing said metal coated topography by pressurizing an inert gas within said annealing chamber to a pressure which exceeds 2.0 atmospheres while heating said metal coated topography to a temperature less than 550°C. to form a first metal silicide of first resistivity upon said substrate dopant region and said polysilicon; and further annealing said first metal silicide by pressurizing an inert gas within said annealing chamber to a pressure which exceeds 2.0 atmospheres while heating said first metal silicide to a temperature less than 750°C. to form a second metal silicide of second resistivity less than said first resistivity upon said substrate dopant region and said polysilicon.