$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Eutectic Cu-alloy wiring structure in a semiconductor device 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/43
출원번호 US-0558524 (1995-11-16)
우선권정보 JP-0281043 (1994-11-16)
발명자 / 주소
  • Miyakawa Kuniko (Tokyo JPX)
출원인 / 주소
  • NEC Corporation (Tokyo JPX 03)
인용정보 피인용 횟수 : 39  인용 특허 : 1

초록 ▼

In a semiconductor device having a wiring groove in alignment with a contact hole, a wiring structure includes a diffusion preventing film formed on the bottom and side walls of the wiring groove, the diffusion preventing film being composed of a barrier metal for preventing diffusion of Cu and an e

대표청구항 ▼

A wiring structure in a semiconductor device having a connection hole in alignment with another connection hole, the wiring structure including a diffusion preventing film formed on the bottom and side walls of each said hole, the diffusion preventing film being composed of a barrier metal for preve

이 특허에 인용된 특허 (1)

  1. Hooper Robert C. (Houston TX) Roane Bobby A. (Manvel TX) Verret Douglas P. (Sugar Land TX), Metal contacts and interconnections for VLSI devices.
    상세보기

이 특허를 인용한 특허 (39)

  1. Pramanick Shekhar ; Brown Dirk ; Iacoponi John A., Dual barrier and conductor deposition in a dual damascene process for semiconductors.
    상세보기
  2. McQueen, Mark, ESD/EOS protection structure for integrated circuit devices and methods of fabricating the same.
    상세보기
  3. Allen McTeer, Formation of electrical contacts to conductive elements in the fabrication of semiconductor integrated circuits.
    상세보기
  4. Nariman Homi E. ; Fulford ; Jr. H. Jim, High-reliability damascene interconnect formation for semiconductor fabrication.
    상세보기
  5. Satitpunwaycha Peter ; Yao Gongda ; Ngan Kenny King-Tai ; Xu Zheng, Integrated PVD system for aluminum hole filling using ionized metal adhesion layer.
    상세보기
  6. Ahn, Kie Y., Integrated circuit wiring with low RC time delay.
    상세보기
  7. Huang, Tsung-Min; Lee, Chung-Ju; Tsai, Tsung-Jung, Interconnect structure and methods of making same.
    상세보기
  8. Huang, Tsung-Min; Lee, Chung-Ju; Tsai, Tsung-Jung, Interconnect structure and methods of making same.
    상세보기
  9. Huang, Tsung-Min; Lee, Chung-Ju; Tsai, Tsung-Jung, Interconnect structure and methods of making same.
    상세보기
  10. Wong,Kwong Hon; Hsu,Louis C.; Dalton,Timothy J.; Radens,Carl J.; Yang,Chih Chao; Clevenger,Lawrence A.; Standaert,Theodorus E., Interconnect structures with encasing cap and methods of making thereof.
    상세보기
  11. Wong,Kwong Hon; Hsu,Louis C.; Dalton,Timothy J.; Radens,Carol; Yang,Chih Chao; Clevenger,Lawrence A.; Standaert,Theodorus E., Interconnect structures with encasing cap and methods of making thereof.
    상세보기
  12. Edward Crandal Cooney, III ; Cyprian Emeka Uzoh, Low resistivity tantalum.
    상세보기
  13. Hsia Shouli Steve ; Wang Zhihai ; Chen Fred,TWX, Metal interconnect stack for integrated circuit structure.
    상세보기
  14. Yamazaki, Shunpei; Shoji, Hironobu; Kawamata, Ikuko, Method for manufacturing display device with electrode having frame shape.
    상세보기
  15. Ahn,Kie Y., Method of fabricating a semiconductor interconnect structure.
    상세보기
  16. Lu, Chih Wei; Lee, Chung-Ju, Method of fabricating a semiconductor interconnect structure.
    상세보기
  17. Lu, Chih Wei; Lee, Chung-Ju, Method of fabricating an semiconductor interconnect structure.
    상세보기
  18. Mochizuki Hiroshi,JPX ; Okuwada Kumi,JPX ; Kanaya Hiroyuki,JPX ; Hidaka Osamu,JPX ; Shuto Susumu,JPX ; Kunishima Iwao,JPX, Method of forming a ferroelectric device.
    상세보기
  19. Barr, Alexander L.; Venkatesan, Suresh; Clegg, David B.; Cole, Rebecca G.; Adetutu, Olubunmi; Greer, Stuart E.; Anthony, Brian G.; Venkatraman, Ramnath; Braeckelmann, Gregor; Reber, Douglas M.; Crown, Method of forming semiconductor device including interconnect barrier layers.
    상세보기
  20. Ahn, Kie Y.; Forbes, Leonard; Farrar, Paul A., Methods and structures for metal interconnections in integrated circuits.
    상세보기
  21. Ahn,Kie Y.; Forbes,Leonard; Farrar,Paul A., Methods and structures for metal interconnections in integrated circuits.
    상세보기
  22. Malta Dean M. ; Dreifus David L., Methods for fabricating microelectronic structures including semiconductor islands.
    상세보기
  23. Lee Byoung-tack,KRX, Methods of forming capacitor electrodes having reduced susceptibility to oxidation.
    상세보기
  24. Bon-Jae Koo KR, Methods of forming ferroelectric memory cells.
    상세보기
  25. Park Young-soh,KRX ; Lee Sang-in,KRX ; Hwang Cheol-seong,KRX ; Hwang Doo-sup,KRX ; Cho Hag-Ju,KRX, Methods of forming integrated circuit capacitors using metal reflow techniques.
    상세보기
  26. Dreifus David L. ; Malta Dean M., Microelectronic structures including semiconductor islands.
    상세보기
  27. Simon, Andrew H.; Uzoh, Cyprian E., Open-bottomed via liner structure and method for fabricating same.
    상세보기
  28. Hsia Shouli Steve ; Wang Zhihai ; Chen Fred,TWX, Process for forming metal interconnect stack for integrated circuit structure.
    상세보기
  29. Collins, Dale W.; Lindgren, Joe, Semiconductor constructions.
    상세보기
  30. Collins, Dale W.; Lindgren, Joe, Semiconductor constructions; and methods for providing electrically conductive material within openings.
    상세보기
  31. Kobayashi, Kazuya; Sano, Yuichi; Tokuda, Daisuke; Tokuya, Hiroaki, Semiconductor device.
    상세보기
  32. Mochizuki Hiroshi,JPX ; Okuwada Kumi,JPX ; Kanaya Hiroyuki,JPX ; Hidaka Osamu,JPX ; Shuto Susumu,JPX ; Kunishima Iwao,JPX, Semiconductor device having ferroelectric capacitor structures.
    상세보기
  33. Tamio Satou JP, Semiconductor device including lead wiring protected by dual barrier films.
    상세보기
  34. Hayashi Yoshihiro,JPX ; Tanabe Nobuhiro,JPX ; Takeuchi Tsuneo,JPX ; Saito Shinobu,JPX, Semiconductor device with conductive plugs.
    상세보기
  35. Hideo Takagi JP; Kiyoshi Izumi JP; Wataru Futo JP; Satoshi Otsuka JP; Shigetaka Uji JP; Masataka Hoshino JP; Yukihiro Satoh JP; Koji Endo JP; Yuzuru Ohta JP; Nobuhiro Misawa JP, Semiconductor device with copper wiring and its manufacture method.
    상세보기
  36. Fukuzumi, Yoshiaki, Semiconductor device with tapered contact hole and wire groove.
    상세보기
  37. Fukuzumi, Yoshiaki, Semiconductor device with tapered contact hole and wire groove.
    상세보기
  38. Fukuzumi,Yoshiaki, Semiconductor device with tapered contact hole and wire groove.
    상세보기
  39. Koo Bon-Jae,KRX, Structure of a ferroelectric memory cell and method of fabricating it.
    상세보기

관련 콘텐츠

섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로