초록 ▼

A method of increasing the performance of an FET device by aligning the channel of the FET with the [110] crystal direction of a {100} silicon wafer. The {100} silicon wafer and the image of a lithographic mask are rotated 45 cc.degree. relative to each other so that, instead of the channel being al

A method of increasing the performance of an FET device by aligning the channel of the FET with the [110] crystal direction of a {100} silicon wafer. The {100} silicon wafer and the image of a lithographic mask are rotated 45 cc.degree. relative to each other so that, instead of the channel being aligned parallel with the [100] crystal direction in the conventional fabrication, the channel is aligned approximately parallel with the [110] crystal direction. The mobility of the carriers is higher in the [110] crystal direction thereby increasing the performance of the FET with only a minor modification in the lithographic process. The novel FET results with its channel aligned approximately parallel with the [110] crystal direction.

대표청구항 ▼

[ Having thus described the invention, what is claimed is:] [1.] In an integrated circuit with at least one field effect transistor (FET) having a source, drain and gate with the source and drain separated by a channel under the gate, comprising:a {100} monocrystalline silicon substrate having (100)

[ Having thus described the invention, what is claimed is:] [1.] In an integrated circuit with at least one field effect transistor (FET) having a source, drain and gate with the source and drain separated by a channel under the gate, comprising:a {100} monocrystalline silicon substrate having (100) and (110) crystal planes and [100] and [110] crystal directions;a FET gate having a length and a width and being insulated from the substrate by a silicon oxide layer thermally grown in the silicon substrate and aligned with the [100] crystal direction, said gate being patterned with the gate width in the [110] crystal direction so that the gate width is aligned approximately orthogonal to the (110) crystal plane and parallel with the [110] crystal direction;a source on one side of said patterned gate width and a drain on the other side of the patterned gate width, with impurities of the source and drain being disposed in the silicon substrate aligned with the [100] crystal direction; anda channel being formed under the gate between the source and drain when voltage is applied and being aligned in a direction parallel with the direction of the gate width, whereby the performance of the FET is enhanced due to a higher mobility of the carriers in the [110] crystal direction and due to the high quality of the silicon oxide layer insulating the gate from the substrate by being disposed in the [100] crystal direction.