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Etch process for single crystal silicon 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • C30B-023/00
출원번호 US-0680809 (1996-07-16)
발명자 / 주소
  • Zhao Ganming
  • Ko Terry K.
  • Chin Weffrey David
출원인 / 주소
  • Applied Materials, Inc.
대리인 / 주소
    Sheldon & Mak
인용정보 피인용 횟수 : 45  인용 특허 : 0

초록

A process for etching shallow trenches in single crystal silicon is described. The process etchant comprises HBr/Cl.sub.2 /O.sub.2 /He. The process can be used with various mask 24 schemes including, for example, photoresists, oxide hardmasks and nitride hardmasks. The process forms shallow trenches

대표청구항

[ What is claimed is:] [7.] A process for etching shallow trenches in single crystal silicon, the process comprising the steps of:(a) placing a single crystal silicon into a chamber;(b) introducing into the chamber a process gas comprising chlorine, bromine, oxygen and an inert gas;(c) generating a

이 특허를 인용한 특허 (45)

  1. Gardner Mark I. ; Gilmer Mark C., Advanced isolation structure for high density semiconductor devices.
  2. Jacobs,Keren; Eppler,Aaron, Etch with ramping.
  3. Yoshida Kazuyoshi,JPX, Etching method.
  4. Allen ; III Tuman Earl, Etching methods, methods of removing portions of material, and methods of forming silicon nitride spacers.
  5. Allen, III, Tuman Earl, Etching methods, methods of removing portions of material, and methods of forming silicon nitride spacers.
  6. Allen, III, Tuman Earl, Etching methods, methods of removing portions of material, and methods of forming silicon nitride spacers.
  7. Allen, III, Tuman Earl, Etching methods, methods of removing portions of material, and methods of forming silicon nitride spacers.
  8. Tuman Earl Allen, III, Etching methods, methods of removing portions of material, and methods of forming silicon nitride spacers.
  9. Tuman Earl Allen, III, Etching methods, methods of removing portions of material, and methods of forming silicon nitride spacers.
  10. Donohoe, Kevin G., Etching of high aspect ratio structures.
  11. Donohoe,Kevin G., Etching of high aspect ration structures.
  12. Chebi, Robert; Lin, Frank; Winniczek, Jaroslaw W.; Chen, Wan-Lin; Moore, Erin; Zheng, Lily; Lassig, Stephan; Bogart, Jeff; Rusu, Camelia, Fabrication of a silicon structure and deep silicon etch with profile control.
  13. McReynolds Darrell, Mechanism for etching a silicon layer in a plasma processing chamber to form deep openings.
  14. Landau Charles Robert, Method and apparatus for managing copy on write operations in a virtual memory.
  15. Tammy Zheng ; Calvin Todd Gabriel ; Edward K. Yeh, Method for a consistent shallow trench etch profile.
  16. Maltabes, John G.; Charles, Alain; Mautz, Karl E.; Petrucci, Joseph, Method for defining alignment marks in a semiconductor wafer.
  17. Xu, Songlin; Kusuki, Takakazu; Qian, Xueyu, Method for enhancing etching of TiSix.
  18. Huang,Kao Su, Method for rounding bottom corners of trench and shallow trench isolation process.
  19. Miller Alan J., Method of achieving top rounding and uniform etch depths while etching shallow trench isolation features.
  20. Miller Alan J. ; Vahedi Vahid, Method of achieving top rounding and uniform etch depths while etching shallow trench isolation features.
  21. Li Li ; Bradley J. Howard, Method of controlling striations and CD loss in contact oxide etch.
  22. Li, Li; Howard, Bradley J., Method of controlling striations and CD loss in contact oxide etch.
  23. Li, Li; Howard, Bradley J., Method of controlling striations and CD loss in contact oxide etch.
  24. Li, Li; Howard, Bradley J., Method of controlling striations and CD loss in contact oxide etch.
  25. Mitsuiki Akira,JPX, Method of etching a layer in a semiconductor device.
  26. Li,Li; Howard,Bradley J., Method of plasma etching a substrate.
  27. Li,Li; Howard,Bradley J., Method of plasma etching a substrate.
  28. Bamnolker, Hanna A.; Yang, Chan Lon; Chowdhury, Saurabu Dutta; Ramkumar, Krishnaswamy T., Methods of forming semiconductor structures having reduced defects, and articles and devices formed thereby.
  29. Allen, III, Tuman Earl, Methods of forming silicon nitride spacers, and methods of forming dielectric sidewall spacers.
  30. Kim,Sun Young, Nonvolatile memory device having STI structure.
  31. Kim, Sun-Young, Nonvolatile memory device having STI structure and method of fabricating the same.
  32. Kanarik, Keren Jacobs; Eppler, Aaron, Photoresist conditioning with hydrogen ramping.
  33. Kanarik,Karen Jacobs; Eppler,Aaron, Photoresist conditioning with hydrogen ramping.
  34. Blalock Guy T. ; Becker David S. ; Donohoe Kevin G., Plasma etching methods.
  35. Blalock,Guy T.; Becker,David S.; Donohoe,Kevin G., Plasma etching methods.
  36. Donohoe, Kevin G.; Stocks, Richard L., Plasma etching methods.
  37. Donohoe, Kevin G.; Stocks, Richard L., Plasma etching methods.
  38. Arita, Kiyoshi; Iwai, Tetsuhiro, Plasma processing method.
  39. Ni, Tuqiang; Jiang, Weinan; Lin, Frank Y.; Huang, Chung-Ho, Plasma processing method and apparatus with control of plasma excitation power.
  40. Satoh Toshihiro,JPX, Semiconductor nonvolatile storage and method of fabricating the same.
  41. Winniczek, Jaroslaw W.; Chebi, Robert P., Silicon etch with passivation using chemical vapor deposition.
  42. Winniczek, Jaroslaw W.; Chebi, Robert P., Silicon etch with passivation using plasma enhanced oxidation.
  43. Lyons Christopher F. ; Bandyopadhyay Basab ; Kepler Nick ; Karlsson Olov ; Wang Larry ; Ibok Effiong, Simplified shallow trench isolation formation with no polish stop.
  44. Shiraishi Yutaka,JPX, Single crystal pulling apparatus, single crystal support mechanism, and single crystal pulling method.
  45. Bian, Zheng, Test pattern for trench poly over-etched step and formation method thereof.
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