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Trench isolation for CMOS devices 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/306
출원번호 US-0918566 (1997-08-22)
발명자 / 주소
  • Akram Salman
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Schwegman, Lundberg, Woessner & Kluth, P.A.
인용정보 피인용 횟수 : 100  인용 특허 : 30

초록 ▼

The present invention is an isolation trench with an insulator, and a method of forming the same using self-aligned processing techniques. The method is implemented with a single mask. A shallow trench is first formed with the mask. Subsequently, the deep trench is formed in self-alignment to the sh

대표청구항 ▼

[ I claim:] [1.] A method of fabricating an isolation region in an integrated circuit, the method comprising:forming a first layer of nitride on a base layer of the integrated circuit;patterning an area of the base layer to define an outline of the isolation region;forming a shallow trench in the pa

이 특허에 인용된 특허 (30)

  1. Prall Kirk (Boise ID), Array of non-volatile sonos memory cells.
    상세보기
  2. Lowrey Tyler A. (Boise ID) Lee Ruojia (Boise ID), Array of read-only memory cells, eacch of which has a one-time, voltage-programmable antifuse element constructed within.
    상세보기
  3. Dennison Charles H. (Boise ID) Doan Trung T. (Boise ID), Arrays of memory integrated circuitry.
    상세보기
  4. Jeng Nanseng (Boise ID), Current leakage reduction at the storage node diffusion region of a stacked-trench DRAM cell by selectively oxidizing th.
    상세보기
  5. Jeng Nanseng (Boise ID), Current leakage reduction at the storage node diffusion region of a stacked-trench dram cell by selectively oxidizing th.
    상세보기
  6. Vo Huy T. (Boise ID), Double sidewall trench capacitor cell.
    상세보기
  7. Violette Michael P. (Boise ID), Dual purpose collector contact and isolation scheme for advanced bicmos processes.
    상세보기
  8. Lee Ruojia (Boise ID) Gonzalez Fernando (Boise ID), Insulated-gate vertical field-effect transistor with high current drive and minimum overlap capacitance.
    상세보기
  9. Lee Ruojia (Boise ID) Gonzalez Fernando (Boise ID), Insulated-gate vertical field-effect transistor with high current drive and minimum overlap capacitance.
    상세보기
  10. Lee Roger R. (Boise ID), Local field enhancement for better programmability of antifuse PROM.
    상세보기
  11. Roberts Ceredig (Boise ID) Reinberg Alan R. (Boise ID), Masking layer having narrow isolated spacings and the method for forming said masking layer and the method for forming n.
    상세보기
  12. Manning Monte (Kuna ID), Method for improving latchup immunity in a dual-polysilicon gate process.
    상세보기
  13. Kameyama Shuichi (Yokohama JPX), Method for manufacturing semiconductor device.
    상세보기
  14. Jeng Nanseng (Boise ID) Harshfield Steven T. (Emmett ID) Schuele Paul J. (Boise ID), Method of forming a contact using a trench and an insulation layer during the formation of a semiconductor device.
    상세보기
  15. Roberts Martin C. (Boise ID), Method of forming a narrow self-aligned, annular opening in a masking layer.
    상세보기
  16. Prall Kirk (Boise ID), Method of forming an array of non-volatile sonos memory cells and array of non-violatile sonos memory cells.
    상세보기
  17. Dennison Charles H. (Boise ID) Doan Trung T. (Boise ID), Method of isolating semiconductor devices and arrays of memory integrated circuitry.
    상세보기
  18. Mathews Viju K. (Boise ID) Dennison Charles H. (Boise ID) Fazan Pierre (Boise ID) Maddox Roy (Boise ID) Ditali Akram (Boise ID), Method of making semiconductor devices having two-layer gate structure.
    상세보기
  19. Figura Thomas A. (Boise ID) Jeng Nanseng (Boise ID), Method of semiconductor device isolation employing polysilicon layer for field oxide formation.
    상세보기
  20. Fazan Pierre (Boise ID) Mathews Viju (Boise ID) Sandhu Gurtej S. (Boise ID) Anjum Mohammed (Boise ID) Chan Hiang C. (Boise ID), Oxidation enhancement in narrow masked field regions of a semiconductor wafer.
    상세보기
  21. Nasr Andre I. (Marlborough MA) Cooperman Steven S. (Southborough MA), Planarization process for IC trench isolation using oxidized polysilicon filler.
    상세보기
  22. Lowrey Tyler A. (Boise ID) Chance Randal W. (Boise ID) Durcan D. Mark (Boise ID) Lee Ruojia (Boise ID) Dennison Charles H. (Boise ID) Liu Yauh-Ching (Boise ID) Fazan Pierre C. (Boise ID) Gonzalez Fer, Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithogr.
    상세보기
  23. Bower Robert W. (Los Gatos CA), Process for forming slots of different types in self-aligned relationship using a latent image mask.
    상세보기
  24. Lee Roger R. (Boise ID) Gonzlez Fernando (Boise ID), Semiconductor processing method for forming substrate isolation trenches.
    상세보기
  25. Fazan Pierre C. (Boise ID) Jeng Nanseng (Boise ID) Dickerson David L. (Boise ID), Semiconductor processing method of forming field oxide regions on a semiconductor substrate utilizing a laterally outwar.
    상세보기
  26. Lee Roger (Boise ID), Shallow trench source EPROM cell.
    상세보기
  27. Fazan Pierre C. (Boise ID) Roberts Martin C. (Boise ID) Sandhu Gurtej S. (Boise ID), Spacers used to form isolation trenches with improved corners.
    상세보기
  28. Seyyedy Mirmajid (Boise ID) Durcan D. Mark (Boise ID), Structure for a semiconductor device comprising conductive trench sidewalls.
    상세보기
  29. Manning Monte (Boise ID), Trench isolation method having a double polysilicon gate formed on mesas.
    상세보기
  30. Manning Monte (Kuna ID), Trench isolation using gated sidewalls.
    상세보기

이 특허를 인용한 특허 (100)

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