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Selective oxide-to-nitride etch process using C.sub.4 F.sub.8 /CO/Ar 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/3065
  • H01L-021/473
출원번호 US-0662754 (1996-06-10)
발명자 / 주소
  • Radens Carl J.
  • Fairchok Cynthia A.
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Schmeiser, Olsen & WattsAnderson
인용정보 피인용 횟수 : 22  인용 특허 : 34

초록

A dry etch process for use in the fabrication of integrated circuits which use SiN etch stop layers is disclosed. The process is conducted in a reactive-ion etch reactor and employs a gaseous etchant mixture comprised of octaflourocyclobutane (C.sub.4 F.sub.8), carbon monoxide (CO) and Ar. The speci

대표청구항

[ We claim:] [1.] A dry etch process for use in the fabrication of an integrated circuit structure having a silicon nitride etch stop layer, said process comprising the steps of:providing a semiconductor wafer having a plurality of gate stacks etched thereon, said gate stacks including a silicon nit

이 특허에 인용된 특허 (34)

  1. Heinz Tony F. (Chappaqua NY) Selwyn Gary S. (Hopewell Junction NY) Singh Syothi (Hopewell Junction NY) Spinetti ; Jr. John A. (Endicott NY), Detection of interfaces with atomic resolution during material processing by optical second harmonic generation.
  2. Kadomura Shingo (Kanagawa JPX), Dry etching method.
  3. Tachi Shinichi (Sayama JPX) Tsujimoto Kazunori (Higashiyamato JPX) Okudaira Sadayuki (Ome JPX) Mukai Kiichiro (Hachioji JPX), Dry etching method.
  4. Tahara Yoshifumi (Machida JPX) Hirano Yoshihisa (Kodaira JPX) Ogasawara Masahiro (Hachioji JPX) Hasegawa Isahiro (Zushi JPX) Horioka Keiji (Kawasaki JPX) Matsushita Takaya (Yokohama JPX), Dry etching method.
  5. Tatsumi Tetsuya (Kanagawa JPX), Dry etching method.
  6. Yanagida Toshiharu (Kanagawa JPX), Dry etching method.
  7. Yamano Atsuhiro (Kawanishi JPX) Tamaki Tokuhiko (Osaka JPX) Kubota Masafumi (Osaka JPX) Harafuji Kenji (Osaka JPX) Nomura Noboru (Kyoto JPX), Drying etching method.
  8. Yew Tri-Rung,TWX ; Liu Meng-Chang,TWX ; Lur Water,TWX ; Sun Shih-Wei,TWX, Dual damascene process.
  9. Poulsen Robert G. (Ottawa CAX) Smith Gerald M. (Ottawa CAX) Westwood William D. (Ottawa CAX), End point control in plasma etching.
  10. Angell David (Poughkeepsie NY) Radens Carl J. (Poughkeepsie NY), End-point detection.
  11. Keswick Peter (Fremont CA) Marks Jeffrey (San Jose CA), Etching titanium nitride using carbon-fluoride and carbon-oxide gas.
  12. Bronner Gary B. (Dutchess County NY) DeBrosse John K. (Chittenden County VT) Mandelman Jack A. (Dutchess County NY), Fabrication process and structure for a contacted-body silicon-on-insulator dynamic random access memory.
  13. Fukase Tadashi (Tokyo JPX) Hamada Takehiko (Tokyo JPX), Fabrication process of a semiconductor device with a wiring structure.
  14. Maydan Dan (Los Altos Hills CA) Somekh Sasson (Redwood City CA) Cheng Mei (San Jose CA) Cheng David (San Jose CA), Magnetron-enhanced plasma etching process.
  15. Koh Chao-Ming (Hsinchu TWX), Method for fabricating a stacked capacitor with a self aligned node contact in a memory cell.
  16. Maniar Papu D. (12618 Olympiad Dr. Austin TX 78759) Blumenthal Roc (6103 Colina La. Austin TX 78759) Klein Jeffrey L. (7511 Step Down Cove Austin TX 78731) Wu Wei (7701 Yaupon Dr. Austin TX 78729), Method for forming a via in a semiconductor device.
  17. Namose Isamu (Suwa JPX), Method of dry etching in semiconductor device processing.
  18. Okamoto Shin,JPX ; Inazawa Kouichiro,JPX ; Furuya Sachiko,JPX ; Koizumi Maki,JPX, Method of etching a substrate.
  19. Tahara Yoshifumi (Yamato JPX) Hirano Yoshihisa (Yokohama JPX) Hasegawa Isahiro (Zushi JPX) Horioka Keiji (Kawasaki JPX), Method of etching object to be processed including oxide or nitride portion.
  20. Trumpp Hans-Joachim (Stuttgart DEX) Greschner Johann (Pliezhausen DEX), Method of making structures with dimensions in the sub-micrometer range.
  21. Sugishima Kenji (Kawasaki JPX) Takada Tadakazu (Kawasaki JPX), Method of manufacturing a semiconductor device.
  22. Sung Hung-Cheng (Kaohsiung TWX) Chen Ling (Sunnyvale CA), Method of manufacturing metallic source line, self-aligned contact for flash memory devices.
  23. Saito Tomohiro (Yokohama JPX) Takahashi Minoru (Yokohama JPX) Yagishita Atsushi (Yokohama JPX), Method of manufacturing thin film transistor.
  24. Nagayama Tetsuji (Kanagawa JPX), Method of producing semiconductor device using a hydrogen-enriched layer.
  25. Chen Lee (Poughkeepsie NY) Khoury Henri A. (Yorktown Heights NY) Seymour Harlan R. (Morton Grove IL), Optical emission spectroscopy end point detection in plasma etching.
  26. Yu Chen-Hua (Keelung TWX) Jang Syun-Ming (Hsin-chu TWX), PECVD silicon nitride for etch stop mask and ozone TEOS pattern sensitivity elimination.
  27. Inazawa Koichiro (Tokyo JPX) Okamoto Shin (Kofu JPX) Hayashi Hisataka (Yokohama JPX) Matsushita Takaya (Yokkaichi JPX), Plasma etching method.
  28. Blalock Guy T. (Boise ID), Plasma treatment of O-rings.
  29. Vogel Diane C. (Fremont CA) Tang Marian C. (Rodeo CA) Reichelderfer Richard F. (Castro Valley CA), Process and gas mixture for etching silicon dioxide and silicon nitride.
  30. Arleo Paul (Menlo Park CA) Henri Jon (San Jose CA) Hills Graham (Los Gatos CA) Wong Jerry (Fremont CA) Wu Robert (Pleasanton CA), Process for forming a via in an integrated circuit structure by etching through an insulation layer while inhibiting spu.
  31. Ide Shigeaki (Yamatokoriyama JPX) Oki Ichiroh (Nara JPX), Process for preparing a silicon nitride insulating film for semiconductor memory device.
  32. Blalock Guy (Boise ID) Becker David S. (Boise ID) Roe Fred (Boise ID), Process for selectively etching a layer of silicon dioxide on an underlying stop layer of silicon nitride.
  33. Armacost Michael D. ; Wagner Tina J. ; Passow Michael L. ; Schepis Dominic J. ; Sendelbach Matthew J. ; Wille William C., Process of etching an oxide layer.
  34. Kirchhoff Markus M.,DEX ; Hanebeck Jochen,DEX, Techniques for etching a silicon dioxide-containing layer.

이 특허를 인용한 특허 (22)

  1. Shyu, Lih-Tien; Tu, Yeur-Luen, Bipolar junction transistor (BJT) base conductor pullback.
  2. Bruce James Allen ; Chapple-Sokol Jonathan Daniel ; Koburger ; III Charles W. ; Lercel Michael James ; Mann Randy William ; Nakos James Spiros ; Prxarik John Joseph ; Peterson Kirk David ; Rankin Jed, Borderless contact to diffusion with respect to gate conductor and methods for fabricating.
  3. Darwin A. Clampitt, Cell capacitors, memory cells, memory arrays, and method of fabrication.
  4. Zolla, Howard Gordon, Feature size reduction in thin film magnetic head using low temperature deposition coating of photolithographically-defined trenches.
  5. Schwarz, Benjamin; Yang, Chan-Lon; Ikeuchi, Kiyoko; Keswick, Peter; Lee, Lien, Gate etch process.
  6. Schwarz,Benjamin; Yang,Chan Lon; Ikeuchi,Kiyoko; Keswick,Peter; Lee,Lien, Gate etch process.
  7. Angela T. Hui ; Tuan Duc Pham ; Mark T. Ramsbey ; Yu Sun, Method and system for providing reduced-sized contacts in a semiconductor device.
  8. Kang, Sean S.; Li, Si Yi; Sadjadi, S. M. Reza, Method for etching silicon carbide.
  9. Ngo Minh Van ; Besser Paul R. ; Liu Yowjuang Bill, Method of forming a local interconnect with improved etch selectivity of silicon dioxide/silicide.
  10. Fei Wang ; Lynne A. Okada ; Ramkumar Subramanian ; Calvin T. Gabriel, Method of making a dual damascene structure without middle stop layer.
  11. Darwin A. Clampitt, Method of producing an etch pattern.
  12. Huang, Chuan-Chieh; Chang, Feng-Yueh; Lin, Chi-Lien, Method to improve via or contact hole profile using an in-situ polymer deposition and strip procedure.
  13. Assefa, Solomon; Costrini, Gregory; Jahnes, Christopher Vincent; Rooks, Michael J.; Sun, Jonathan Zanhong, Methods for fabricating contacts to pillar structures in integrated circuits.
  14. Foote David K. ; Ngo Minh Van ; Chan Darin A., Methods for making a semiconductor device with improved hot carrier lifetime.
  15. Jianmin Qiao ; Sanjay Thekdi ; Manuj Rathor ; James E. Nulty, Plasma etch chemistry and method of improving etch control.
  16. Nambu Hidetaka,JPX, Plasma etching method for forming hole in masked silicon dioxide.
  17. Li,Si Yi; Sadjadi,S. M. Reza; Tietz,James V., Plasma etching of silicon carbide.
  18. Chan-Lon Yang ; Dan Arnzen ; Jim Nulty, Selective SAC etch process.
  19. Li,Tingkai; Hsu,Sheng Teng; Ulrich,Bruce D.; Burgholzer,Mark A.; Hill,Ray A., Selective etching processes of silicon nitride and indium oxide thin films for FeRAM device applications.
  20. Yin, Zhiping; Sandhu, Gurtej Singh, Surface treatment of DARC films to reduce defects in subsequent cap layers.
  21. Douglas Blaine Butler, Technique for forming a borderless overlapping gate and diffusion contact structure in integrated circuit device processing.
  22. Lee,Sangheon; Kang,Sean S.; Sadjadi,S M Reza; Deshmukh,Subhash; Kim,Ji Soo, Treatment for corrosion in substrate processing.
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