초록 ▼

A DRAM controller is incorporated onto an existing microcontroller architecture. Existing chip select signals or other signals on the microcontroller are multiplexed with RAS and CAS signals. The RAS and CAS signals are asserted when an address is within a specific programmable address range and DRA

A DRAM controller is incorporated onto an existing microcontroller architecture. Existing chip select signals or other signals on the microcontroller are multiplexed with RAS and CAS signals. The RAS and CAS signals are asserted when an address is within a specific programmable address range and DRAM mode is enabled. The pins selected for RAS and CAS provide regular signals such as chip selects when not in DRAM mode. The timing of the chip select signal signals are adjusted when the chip select signals are utilized as column and row address strobes. Additionally, multiplexed addresses are provided from the microcontroller as well as refresh control. The microcontroller can provide high byte and low byte access by providing an upper column address strobe signal (UCAS) to support access for high byte and word access and a lower column address strobe signal (LCAS) to support low byte and word access. Mid range chip selects provide the UCAS and LCAS signals. A lower chip select signal (LCS) may provide a first RAS signal which is active in a first DRAM mode. The LCS signal is asserted as a first RAS signal when an address within a programmable memory range and the first DRAM mode is enabled. A second RAS signal provides access to a DRAM mapped into the upper half of memory. A mid range chip select pin is multiplexed with the second RAS signal.

대표청구항 ▼

[ What is claimed is:] [1.] A processor comprising:a first circuit, responsive to a first value of a first programmable DRAM mode control signal and a first address range, to generate on a first output terminal of the processor a first row address strobe (RAS) signal for a DRAM mapped into the first

[ What is claimed is:] [1.] A processor comprising:a first circuit, responsive to a first value of a first programmable DRAM mode control signal and a first address range, to generate on a first output terminal of the processor a first row address strobe (RAS) signal for a DRAM mapped into the first address range,wherein the first circuit is responsive to a second value of the first programmable DRAM mode control signal and the first address range to generate a first non-DRAM control signal on the first output terminal;a second circuit responsive to a first value of a second programmable DRAM mode control signal and a second address range, to generate on a second output terminal of the processor a second row address strobe (RAS) signal for a DRAM mapped into the second address range,wherein the second circuit is responsive to a second value of the second programmable DRAM mode control signal and the second address range to generate a second non-DRAM control signal on the second output terminal; anda third circuit responsive to the first address range and the first value of the first DRAM mode control signal to generate on a third output terminal of the processor a column address strobe (CAS) signal for the DRAM mapped into the first address space, the third circuit also being responsive to the second address range and the first value of the second DRAM mode control signal to generate on the third output terminal of the processor the column address strobe (CAS) signal for the DRAM mapped into the second address space.