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Apparatus for creating strong interface between in-situ SACVD and PECVD silicon oxide films 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H05H-001/00
  • C23C-016/00
출원번호 US-0740969 (1996-11-05)
발명자 / 주소
  • Robles Stuardo
  • Sivaramakrishnan Visweswaren
  • Galiano Maria
  • Kithcart Victoria
출원인 / 주소
  • Applied Materials, Inc.
대리인 / 주소
    Townsend & Townsend & Crew
인용정보 피인용 횟수 : 18  인용 특허 : 12

초록

A method and apparatus for ramping down the deposition pressure in a SACVD process. The present invention also provides a method and apparatus for subsequently ramping up the pressure for a PECVD process in such a manner as to prevent unwanted reactions which could form a weak interlayer interface.

대표청구항

[ What is claimed is:] [1.] A chemical vapor deposition apparatus comprising:a substrate processing chamber;a substrate support configured to hold a substrate in said substrate processing chamber during a chemical vapor deposition operation;a gas distribution system configured to introduce gases int

이 특허에 인용된 특허 (12)

  1. Wang David N. (Cupertino CA) White John M. (Hayward CA) Law Kam S. (Union City CA) Leung Cissy (Union City CA) Umotoy Salvador P. (Pittsburg CA) Collins Kenneth S. (San Jose CA) Adamik John A. (San R, CVD of silicon oxide using TEOS decomposition and in-situ planarization process.
  2. Ikeda Yasuo (Tokyo JPX), Chemical vapor deposition method for forming SiO2.
  3. Moghadam Farhad K. (Los Gatos CA), Dielectric deposition and cleaning process for improved gap filling and device planarization.
  4. Cain John (Schertz TX) Fujishiro Felix (San Antonio TX) Lee Chang-Ou (San Antonio TX) Koenigseder Sigmund (San Antonio TX) Vines Landon (San Antonio TX), Integrated-circuit processing with progressive intermetal-dielectric deposition.
  5. Hsia Shaw-Tzeng (Taipei TWX) Chen Kuang-Chao (Taipei TWX), Inter-metal-dielectric planarization process.
  6. Ikeda Yasuo (Tokyo JPX), Method and apparatus for forming silicon oxide film by chemical vapor deposition.
  7. Kwok Kurt (Mountain View CA) Robertson Robert (Palo Alto CA), Method for depositing ozone/TEOS silicon oxide films of reduced surface sensitivity.
  8. Kasagi Yasuo (Tokyo JPX), Method for forming electrical contacts in a semiconductor device.
  9. Wang Chih C. (Hightstown NJ) Bates Ronald F. (Trenton NJ), Method of depositing an abrasive layer.
  10. Wang David N. (Cupertino CA) White John M. (Hayward CA) Law Kam S. (Union City CA) Leung Cissy (Union City CA) Umotoy Salvador P. (Pittsburg CA) Collins Kenneth S. (San Jose CA) Adamik John A. (San R, Plasma-enhanced CVD process using TEOS for depositing silicon oxide.
  11. Matsuura Masazumi (Hyogo JPX), Semiconductor device having an interlayer insulating film of high crack resistance.
  12. Wang David N. (Cupertino) White John M. (Hayward) Law Kam S. (Union City) Leung Cissy (Union City) Umotoy Salvador P. (Pittsburg) Collins Kenneth S. (San Jose) Adamik John A. (San Ramon) Perlov Ilya , Thermal CVD/PECVD reactor and use for thermal chemical vapor deposition of silicon dioxide and in-situ multi-step planar.

이 특허를 인용한 특허 (18)

  1. Shamouil Shamouilian ; Mehran Moalem ; Tony S. Kaushal, Abatement of fluorine gas from effluent.
  2. Shamouilian, Shamouil; Kaushal, Tony S., Abatement of hazardous gases in effluent.
  3. Yen Wen-Ping,TWX ; Ku Chia-Lin,TWX ; Lee Chong-Che,TWX, Additional buffer layer for eliminating ozone/tetraethylorthosilicate sensitivity on an arbitrary trench structure.
  4. Ferron, Shawn; Kelly, John; Vermeulen, Robbert, Apparatus and method for controlled combustion of gaseous pollutants.
  5. Yudovsky, Joseph; Griffin, Kevin; Gangakhedkar, Kaushal, Apparatus and methods for injector to substrate gap control.
  6. Hong, Sukwon; Tran, Toan; Mallick, Abhijit; Liang, Jingmei; Ingle, Nitin K., Low shrinkage dielectric films.
  7. Srinivasan, Anand; Sandhu, Gurtej; Iyer, Ravi, Method of forming fluorine doped boron-phosphorous silicate glass (F-BPSG) insulating materials.
  8. Lee,Jae Suk, Method of forming pre-metal dielectric layer.
  9. Clark, Daniel O.; Raoux, Sebastien; Vermeulen, Robert M.; Crawford, Shaun W., Methods and apparatus for sensing characteristics of the contents of a process abatement reactor.
  10. Swaminathan, Shankar; Kang, Hu; LaVoie, Adrien, Methods for modulating step coverage during conformal film deposition.
  11. Srinivasan, Anand; Sandhu, Gurtej; Iyer, Ravi, Methods of forming fluorine doped insulating materials.
  12. Terry Alan Breeden ; Iraj Eric Shahvandi ; Michael Thomas Tucker ; Olivier Gerard Marc Vatel ; Karl Emerson Mautz ; Ralf Zedlitz DE, Plasma-enhanced chemical vapor deposition (CVD) method to fill a trench in a semiconductor substrate.
  13. Chiu, Ho-Man Rodney; Clark, Daniel O.; Crawford, Shaun W.; Jung, Jay J.; Todd, Leonard B.; Vermeulen, Robbert, Reactor design to reduce particle deposition during process abatement.
  14. Rossman, Kent, Staggered in-situ deposition and etching of a dielectric layer for HDP CVD.
  15. Rossman,Kent, Staggered in-situ deposition and etching of a dielectric layer for HDP CVD.
  16. Rossman, Kent, Staggered in-situ deposition and etching of a dielectric layer for HDP-CVD.
  17. Rossman,Kent, Staggered in-situ deposition and etching of a dielectric layer for HDP-CVD.
  18. Kitano, Takahiro; Kobayashi, Shinji; Esaki, Yukihiko; Morikawa, Masateru, Substrate processing unit and processing method.
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