초록 ▼

A BiCMOS integrated circuit is fabricated using a minimum number of wafer processing steps and yet offers the IC circuit designer five (5) different transistor types. These types include P-channel and N-channel MOS transistors and three different bipolar transistors whose emitters are all formed by

A BiCMOS integrated circuit is fabricated using a minimum number of wafer processing steps and yet offers the IC circuit designer five (5) different transistor types. These types include P-channel and N-channel MOS transistors and three different bipolar transistors whose emitters are all formed by a different process and all are characterized by different current gains and different breakdown voltages. A differential silicon dioxide/silicon nitride masking technique is used in the IC fabrication process wherein both P-type buried layers (PBL) and N-type buried layers (NBL) are formed in a silicon substrate using a single mask set and further wherein P-type wells and N-type wells are formed above these buried layers in an epitaxial layer, also using a single SiO.sub.2 /Si.sub.3 N.sub.4 differential mask set. Two of the bipolar transistor emitters are formed by out diffusion from first and second levels of polysilicon, whereas the emitter of the third bipolar transistor is formed by ion implantation doping.

대표청구항 ▼

[ We claim:] [1.] A bipolar/complementary metal-oxide-silicon (BiCMOS) integrated circuit structure including a silicon substrate having N-type buried layers and P-type buried layers therein and an epitaxial layer disposed above the N-type buried layers and P-type buried layers and having different

[ We claim:] [1.] A bipolar/complementary metal-oxide-silicon (BiCMOS) integrated circuit structure including a silicon substrate having N-type buried layers and P-type buried layers therein and an epitaxial layer disposed above the N-type buried layers and P-type buried layers and having different conductivity type wells formed therein; N-channel and P-channel MOS transistors formed in different conductivity type wells in the epitaxial layer and having transistor gate regions formed of a first level of polysilicon; a bipolar transistor formed in yet another well in the epitaxial layer and having collector, base and emitter regions within the well, with the emitter region being connected directly to either a first level or a second level of polysilicon and created by impurities received by out-diffusion from either the first or second levels of polysilicon; a second bipolar transistor formed in still another well within the epitaxial layer and having its emitter region formed by contact to either the first or second levels of polysilicon and out-diffusion of impurities therefrom; and yet a further bipolar transistor formed in a further well within the epitaxial layer and having its emitter region formed by ion implantation into the surface of the epitaxial layer.