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Positive charge pump 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G05F-001/10
출원번호 US-0946727 (1997-10-08)
우선권정보 EP-0830521 (1996-10-11)
발명자 / 주소
  • Ghilardelli Andrea,ITX
  • Mulatti Jacopo,ITX
  • Ghezzi Stefano,ITX
출원인 / 주소
  • SGS-Thomson Microelectronics S.r.l., ITX
대리인 / 주소
    Wolf, Greenfield & Sacks, P.C.Morris
인용정보 피인용 횟수 : 54  인용 특허 : 4

초록

A charge pump comprises a plurality of stages connected in series, an input terminal of the charge pump being connected to a voltage supply and an output terminal of the charge pump providing an output voltage higher than the voltage supply. Each stage comprises unidirectional current flow MOS trans

대표청구항

[ What is claimed is:] [1.] Charge pump comprising a plurality of stages connected in series, an input terminal of the charge pump being connected to a voltage supply and an output terminal of the charge pump providing an output voltage higher than the voltage supply, each stage comprising unidirect

이 특허에 인용된 특허 (4)

  1. Olivo Marco (Bergamo ITX) Pascucci Luigi (Sesto S. Giovanni ITX) Villa Corrado (Sovico ITX), CMOS voltage multiplier.
  2. Wong Stephen L. (Scarsdale NY), Integrated charge pump circuit with back bias voltage reduction.
  3. Arakawa Hideki (Kanagawa JPX), Voltage booster circuit.
  4. Kassapian Christian G. (Marseille FRX), Voltage booster circuit of the charge-pump type with bootstrapped oscillator.

이 특허를 인용한 특허 (54)

  1. Merritt, Todd A.; Butler, Hal W., Apparatus and method for generating an oscillating signal.
  2. Dadashev, Oleg; Betser, Yoram; Maayan, Eduardo, Apparatus and methods for multi-level sensing in a memory array.
  3. Oku, Satoru, Booster, IC card having the same, and electronic equipment having the same.
  4. Shor, Joseph S.; Maayan, Eduardo; Polansky, Yan, Charge pump stage with body effect minimization.
  5. Shor, Joseph S.; Maayan, Eduardo; Polansky, Yan, Charge pump stage with body effect minimization.
  6. Shor, Joseph; Sofer, Yair; Maayan, Eduardo, Charge pump with constant boosted output voltage.
  7. Mauro Zanuccoli IT; Roberto Canegallo IT; Davide Dozza IT, Charge pump with efficient switching techniques.
  8. McPartland Richard Joseph ; Banerjee Amit Kumar ; Loeper Duane J., Charge pump with no diode drop at output stage.
  9. Kushnarenko, Alexander, Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same.
  10. Shappir, Assaf, Contact in planar NROM technology.
  11. Bloom, Ilan; Eitan, Boaz; Irani, Rustom, Dense non-volatile memory array and method of fabrication.
  12. Maayan, Eduardo, Device to program adjacent storage cells of different NROM cells.
  13. Irani, Rustom; Eitan, Boaz; Bloom, Ilan; Shappir, Assaf, Double density NROM with nitride strips (DDNS).
  14. Betser,Yoram; Maayan,Eduardo; Sofer,Yair, Dynamic matching of signal path and reference path for sensing.
  15. Sofer,Yair; Maayan,Eduardo; Betser,Yoram, Dynamic matching of signal path and reference path for sensing.
  16. Shor, Joseph S.; Polansky, Yan, Fast discharge for program and verification.
  17. Merritt, Todd A., High output high efficiency low voltage charge pump.
  18. Merritt, Todd A.; Batra, Shubneesh, High output high efficiency low voltage charge pump.
  19. Toshiya Sato JP, High speed voltage boosting circuit.
  20. Tz-yi Liu, High voltage charge pump circuits.
  21. Kushnarenko,Alexander, High voltage low power driver.
  22. Mauro Zanuccoli IT; Roberto Canegallo IT; Davide Dozza IT, High-efficiency bidirectional voltage boosting device.
  23. Shor,Joseph S.; Maayan,Eduardo; Betser,Yoram, MOS capacitor with reduced parasitic capacitance.
  24. Betser, Yoram; Kushnarenko, Alexander; Dadashev, Oleg, Measuring and controlling current consumption and output current of charge pumps.
  25. Polansky, Yan; Lavan, Avi, Memory array programming circuit and a method for using the circuit.
  26. Dadashev,Oleg, Method and apparatus for measuring charge pump output current.
  27. Shor, Joseph S.; Harush, Avri; Eisen, Shai, Method and circuit for operating a memory cell using a single charge pump.
  28. Egerer, Jens, Method and integrated circuit for boosting a voltage.
  29. Betser,Yoram; Sofer,Yair; Maayan,Eduardo, Method circuit and system for compensating for temperature induced margin loss in non-volatile memory cells.
  30. Maayan, Eduardo; Eitan, Boaz; Lann, Ameet, Method for programming a reference cell.
  31. Maayan,Eduardo; Eliyahu,Ron; Lann,Ameet; Eitan,Boaz, Method for programming a reference cell.
  32. Lusky, Eli; Eitan, Boaz, Method of erasing non-volatile memory cells.
  33. Eitan, Boaz; Shainsky, Natalie, Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection.
  34. Shappir, Assaf; Bloom, Ilan; Eitan, Boaz, Method, circuit and system for erasing one or more non-volatile memory cells.
  35. Shappir,Assaf; Eisen,Shai, Method, circuit and systems for erasing one or more non-volatile memory cells.
  36. Cohen, Guy; Polansky, Yan, Method, system and circuit for programming a non-volatile memory array.
  37. Cohen,Guy, Method, system, and circuit for operating a non-volatile memory array.
  38. Shappir,Assaf; Avni,Dror; Eitan,Boaz, Method, system, and circuit for operating a non-volatile memory array.
  39. Eitan, Boaz; Shainsky, Natalie, NROM non-volatile memory and mode of operation.
  40. Eitan,Boaz, Non-volatile memory cell and non-volatile memory devices.
  41. Lusky, Eli; Shappir, Assaf; Irani, Rustom; Eitan, Boaz, Non-volatile memory structure and method of fabrication.
  42. Lusky,Eli; Eitan,Boaz; Cohen,Guy; Maayan,Eduardo, Operating array cells with matched reference cells.
  43. Shor, Joseph S., Operational amplifier with fast rise time.
  44. Shappir,Assaf; Eisen,Shai, Partial erase verify.
  45. Shor,Joseph S.; Betser,Yoram; Sofer,Yair, Power-up and BGREF circuitry.
  46. Lusky,Eli; Bloom,Ilan; Shappir,Assaf; Eitan,Boaz, Protection of NROM devices from charge damage.
  47. Oliver, Ronald A.; Diorio, Christopher J., RFID tags with power rectifiers that have bias.
  48. Oliver, Ronald A.; Diorio, Christopher J., RFID tags with power rectifiers that have bias.
  49. Sofer,Yair; Elyada,Ori; Betser,Yoram, Replenishment for internal voltage.
  50. Eitan, Boaz, Secondary injection for NROM.
  51. Shor, Joseph S.; Maayan, Eduardo, Stack element circuit.
  52. Kushnarenko, Alexander; Nitzan, Ifat, System and method for regulating loading on an integrated circuit power supply.
  53. Lipka, Ronald J.; Garlapati, Akhil K., Ultrahigh voltage charge pump apparatus implemented with low voltage technology.
  54. Butler, Hal, Voltage charge pump with circuit to prevent pass device latch-up.
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