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NMOS negative charge pump 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G05F-003/02
출원번호 US-0012331 (1998-01-23)
우선권정보 EP-0080014 (1997-01-23)
발명자 / 주소
  • Ghilardelli Andrea,ITX
  • Mulatti Jacopo,ITX
  • Branchetti Maurizio,ITX
출원인 / 주소
  • STMicroelectronics S.r.l., ITX
대리인 / 주소
    Galanthay
인용정보 피인용 횟수 : 78  인용 특허 : 3

초록

A negative charge pump circuit comprises a plurality of charge pump stages connected in series to each other. Each stage has a stage input terminal and a stage output terminal. A first stage has the stage input terminal connected to a reference voltage, a final stage has the stage output terminal op

대표청구항

[ What is claimed is:] [1.] Negative charge pump circuit comprising:a plurality of charge pump stages connected in series to each other, each stage having a stage input terminal and a stage output terminal, said plurality of stages comprising a first stage having the respective stage input terminal

이 특허에 인용된 특허 (3)

  1. Olivo Marco (Bergamo ITX) Pascucci Luigi (Sesto S. Giovanni ITX) Villa Corrado (Sovico ITX), CMOS voltage multiplier.
  2. Chang Chung K. (Sunnyvale CA) Chen Johnny C. (Cupertino CA) Cleveland Lee E. (Santa Clara CA), Low supply voltage negative charge pump.
  3. Arakawa Hideki (Kanagawa JPX), Voltage booster circuit.

이 특허를 인용한 특허 (78)

  1. Hawley,Frank W.; Issaq,A. Farid; McCollum,John L.; Gangopadhyay,Shubhra M.; Lubguban,Jorge A.; Shen,Jin Miao, Amorphous carbon metal-to-metal antifuse with adhesion promoting layers.
  2. Dadashev, Oleg; Betser, Yoram; Maayan, Eduardo, Apparatus and methods for multi-level sensing in a memory array.
  3. Hu, Chih-Ting; Hung, Chun-Hsiung; Peng, Wu-Chin; Chang, Kuen-Long; Chen, Ken-Hui, Apparatus of supplying power while maintaining its output power signal and method therefor.
  4. Wei,Andy C.; Wristers,Derick J.; Fuselier,Mark B., Biased, triple-well fully depleted SOI structure.
  5. Wei, Andy C.; Wristers, Derick J.; Fuselier, Mark B., Biased, triple-well fully depleted SOI structure, and various methods of making and operating same.
  6. Yamahira, Seiji, Booster circuit.
  7. Ayel, François, Charge pump circuit for generating a negative voltage.
  8. Shor, Joseph S.; Maayan, Eduardo; Polansky, Yan, Charge pump stage with body effect minimization.
  9. Shor, Joseph S.; Maayan, Eduardo; Polansky, Yan, Charge pump stage with body effect minimization.
  10. Shor, Joseph; Sofer, Yair; Maayan, Eduardo, Charge pump with constant boosted output voltage.
  11. Kushnarenko, Alexander, Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same.
  12. Shappir, Assaf, Contact in planar NROM technology.
  13. Bloom, Ilan; Eitan, Boaz; Irani, Rustom, Dense non-volatile memory array and method of fabrication.
  14. Maayan, Eduardo, Device to program adjacent storage cells of different NROM cells.
  15. Englekirk, Robert Mark, Differential charge pump.
  16. Irani, Rustom; Eitan, Boaz; Bloom, Ilan; Shappir, Assaf, Double density NROM with nitride strips (DDNS).
  17. Betser,Yoram; Maayan,Eduardo; Sofer,Yair, Dynamic matching of signal path and reference path for sensing.
  18. Sofer,Yair; Maayan,Eduardo; Betser,Yoram, Dynamic matching of signal path and reference path for sensing.
  19. Shor, Joseph S.; Polansky, Yan, Fast discharge for program and verification.
  20. Nadimpalli, Praveen Varma, High efficiency negative regulated charge-pump.
  21. Park, Ki-Tae; Koji, Shimeno; Ogura, Tomoko, High efficiency triple well charge pump circuit.
  22. Kushnarenko,Alexander, High voltage low power driver.
  23. Swonger, James W., High voltage ring pump with inverter stages and voltage boosting stages.
  24. Swonger, James W., High voltage ring pump with inverter stages and voltage boosting stages.
  25. Nobbe, Dan William; Olson, Chris; Kovac, David, Hot carrier injection compensation.
  26. Chung, In Sool; Kim, Seong Dong, Image sensor with improved dynamic range by applying negative voltage to unit pixel.
  27. Burgener, Mark L.; Cable, James S., Integrated RF front end with stacked transistor switch.
  28. Burgener, Mark L.; Cable, James S., Integrated RF front end with stacked transistor switch.
  29. Burgener, Mark L.; Cable, James S., Integrated RF front end with stacked transistor switch.
  30. Burgener, Mark L.; Cable, James S., Integrated RF front end with stacked transistor switch.
  31. Burgener, Mark L.; Cable, James S., Integrated RF front end with stacked transistor switch.
  32. Burgener, Mark L.; Kelly, Dylan J.; Cable, James S., Low noise charge pump method and apparatus.
  33. Burgener, Mark L.; Kelly, Dylan J.; Cable, James S., Low noise charge pump method and apparatus.
  34. Burgener, Mark L.; Kelly, Dylan; Cable, James S., Low noise charge pump method and apparatus.
  35. Kim, Tae Youn; Englekirk, Robert Mark; Kelly, Dylan J., Low-noise high efficiency bias generation circuits and method.
  36. Kim, Tae Youn; Englekirk, Robert Mark; Kelly, Dylan J., Low-noise high efficiency bias generation circuits and method.
  37. Shor,Joseph S.; Maayan,Eduardo; Betser,Yoram, MOS capacitor with reduced parasitic capacitance.
  38. Betser, Yoram; Kushnarenko, Alexander; Dadashev, Oleg, Measuring and controlling current consumption and output current of charge pumps.
  39. Polansky, Yan; Lavan, Avi, Memory array programming circuit and a method for using the circuit.
  40. Dadashev,Oleg, Method and apparatus for measuring charge pump output current.
  41. Shor, Joseph S.; Harush, Avri; Eisen, Shai, Method and circuit for operating a memory cell using a single charge pump.
  42. Betser,Yoram; Sofer,Yair; Maayan,Eduardo, Method circuit and system for compensating for temperature induced margin loss in non-volatile memory cells.
  43. Maayan, Eduardo; Eitan, Boaz; Lann, Ameet, Method for programming a reference cell.
  44. Maayan,Eduardo; Eliyahu,Ron; Lann,Ameet; Eitan,Boaz, Method for programming a reference cell.
  45. Lusky, Eli; Eitan, Boaz, Method of erasing non-volatile memory cells.
  46. Eitan, Boaz; Shainsky, Natalie, Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection.
  47. Shappir, Assaf; Bloom, Ilan; Eitan, Boaz, Method, circuit and system for erasing one or more non-volatile memory cells.
  48. Shappir,Assaf; Eisen,Shai, Method, circuit and systems for erasing one or more non-volatile memory cells.
  49. Cohen, Guy; Polansky, Yan, Method, system and circuit for programming a non-volatile memory array.
  50. Cohen,Guy, Method, system, and circuit for operating a non-volatile memory array.
  51. Shappir,Assaf; Avni,Dror; Eitan,Boaz, Method, system, and circuit for operating a non-volatile memory array.
  52. Eitan, Boaz; Shainsky, Natalie, NROM non-volatile memory and mode of operation.
  53. Snowdon, Kenneth P., Negative charge pump.
  54. Torrisi, Davide; Martines, Ignazio, Negative charge pump architecture with self-generated boosted phases.
  55. Oddone, Giorgio; Frulio, Massimiliano; Figini, Luca; Tassan Caser, Fabio, Negative charge pump with bulk biasing.
  56. Eitan,Boaz, Non-volatile memory cell and non-volatile memory devices.
  57. Lusky, Eli; Shappir, Assaf; Irani, Rustom; Eitan, Boaz, Non-volatile memory structure and method of fabrication.
  58. Lusky,Eli; Eitan,Boaz; Cohen,Guy; Maayan,Eduardo, Operating array cells with matched reference cells.
  59. Shor, Joseph S., Operational amplifier with fast rise time.
  60. Chou, Shao Yu, Output stage of a charge pump circuit providing relatively stable output voltage without voltage degradation.
  61. Le, Thien, P-channel negative pumps.
  62. Shappir,Assaf; Eisen,Shai, Partial erase verify.
  63. Shor,Joseph S.; Betser,Yoram; Sofer,Yair, Power-up and BGREF circuitry.
  64. Scratchley,Douglas A.; Hayek,Charles F.; Graetz,Ernest Frank John, Precision, low drift, stacked voltage reference.
  65. Lusky,Eli; Bloom,Ilan; Shappir,Assaf; Eitan,Boaz, Protection of NROM devices from charge damage.
  66. Sofer,Yair; Elyada,Ori; Betser,Yoram, Replenishment for internal voltage.
  67. Issaq,A. Farid; Hawley,Frank; McCollum,John, Reprogrammable metal-to-metal antifuse employing carbon-containing antifuse material.
  68. Issaq,A. Farid; Hawley,Frank; McCollum,John, Reprogrammable metal-to-metal antifuse employing carbon-containing antifuse material.
  69. Eitan, Boaz, Secondary injection for NROM.
  70. Shor, Joseph S.; Maayan, Eduardo, Stack element circuit.
  71. Burgener, Mark L.; Cable, James S., Switch circuit and method of switching radio frequency signals.
  72. Burgener, Mark L.; Cable, James S., Switch circuit and method of switching radio frequency signals.
  73. Issaq,A. Farid; Hawley,Frank, Switching ratio and on-state resistance of an antifuse programmed below 5 mA and having a Ta or TaN barrier metal layer.
  74. Kushnarenko, Alexander; Nitzan, Ifat, System and method for regulating loading on an integrated circuit power supply.
  75. Englekirk, Robert Mark, Tuning capacitance to enhance FET stack voltage withstand.
  76. Englekirk, Robert Mark, Tuning capacitance to enhance FET stack voltage withstand.
  77. Englekirk, Robert Mark, Variable frequency charge pump.
  78. Tobita,Youichi, Voltage generating circuit.
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