초록 ▼

A method of fabricating ultra shallow junction MOSFET is disclosed. The method comprises following steps. First of all, a semiconductor substrate having gate region and source/drain regions defined are prepared. A IMP process is then performed to anisotropic deposit silicon layer on the top surfaces

A method of fabricating ultra shallow junction MOSFET is disclosed. The method comprises following steps. First of all, a semiconductor substrate having gate region and source/drain regions defined are prepared. A IMP process is then performed to anisotropic deposit silicon layer on the top surfaces of the gate region, source/drain regions. No silicon layer is formed on the sidewall of the gate region. A LDD ion implant into IMP silicon layer is then performed. A thermal oxidation process is then performed to partially oxidize a portion of IMP silicon layer and the sidewall polysilicon of the polygate region to ensure the polygate region is isolated from the source/drain regions. Furthermore, the impurities will be driven into semiconductor substrate to form ultra-shallow junction. After that, a CVD insulating layer is formed on all areas. An anisotropic etching is then performed to form sidewall spacers and expose the remnant IMP silicon layer on both source/drain regions and gate region. Thereafter, a heavily doped ion implantation through IMP silicon layer into semiconductor substrate is carried out. A salicide process is then performed to form silicide layer on the source/drain regions and on the gate region and activate the conductive impurities to form deep junction.

대표청구항 ▼

[ What is claim is:] [1.]1. A method of making ultra shallow junction MOSFET, said method comprising the steps of:providing a semiconductor substrate having source/drain regions and poly-gate region formed thereon;depositing an IMP silicon layer on said source/drain regions and a polysilicon layer o

[ What is claim is:] [1.]1. A method of making ultra shallow junction MOSFET, said method comprising the steps of:providing a semiconductor substrate having source/drain regions and poly-gate region formed thereon;depositing an IMP silicon layer on said source/drain regions and a polysilicon layer on said polygate region using ion-metal plasma directional;performing a first ion implantation to entire areas;performing a thermal oxidation process to form an IMP oxide layer on said source/drain regions and said polysilicon layer by partially oxidizing said IMP silicon layer, said polysilicon layer;forming a dielectric layer on entire areas;performing an anisotropic etching so as to form sidewall spacers on said poly-gate and to do IMP oxide layer removal;performing a second ion implantation through said IMP silicon into said source/drain regions;forming metal layer on entire areas;performing a thermal annealing process so as to form a metal silicide layer on surfaces of said source/drain regions and said polygate region; andremoving unreactive metal layer.