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[미국특허] Digital dual-loop DLL design using coarse and fine loops 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03D-003/24
출원번호 US-0585035 (2000-06-01)
발명자 / 주소
  • R. Jacob Baker
  • Feng Lin
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Schwegman, Lundberg, Woessner & Kluth P.A.
인용정보 피인용 횟수 : 75  인용 특허 : 8

초록 ▼

A dual-loop digital delay locked loop (DLL) is provided. The DLL includes a coarse loop to produce a first delayed signal and provides a wide frequency lock range. The DLL further includes a fine loop connected to the coarse loop to produce a second delayed signal and provides a tight locking. This

대표청구항 ▼

1. A delay locked loop system comprising:a coarse loop to produce a first delayed signal, the coarse loop including a delay range and including: a phase detector; a shift register connected to the phase detector, the shift register including a plurality of register cells; a delay line including a pl

이 특허에 인용된 특허 (8)

  1. Hjerpe James J. (San Diego CA) Russell J. Dennis (LaMesa CA) Young Rocky M. Y. (Escondido CA), All digital phase locked loop.
    상세보기
  2. Saitoh Tetsuo (Kanagawa JPX) Matsuo Syuji (Kanagawa JPX) Taniyoshi Itsurou (Kanagawa JPX) Kitamura Koichi (Kanagawa JPX), Digital phase locked loop having coarse and fine stepsize variable delay lines.
    상세보기
  3. Andresen Bernhard H. (Dallas TX) Casasanta Joseph A. (Allen TX) Keeney Stanley C. (Dallas TX) Martin Robert C. (Dallas TX) Satoh Yoshinori (Plano TX), High performance digital phase locked loop.
    상세보기
  4. Kondo Takako,JPX, Internal clock generator that minimizes the phase difference between an external clock signal and an internal clock signal.
    상세보기
  5. Keeth Brent ; Manning Troy A., Method and apparatus for adjusting the timing of signals over fine and coarse ranges.
    상세보기
  6. Jefferson David E. ; Cope L. Todd,MYX ; Reddy Srinivas ; Cliff Richard G., Programmable logic integrated circuit with on-chip DLL or PLL for clock distribution.
    상세보기
  7. Jefferson David E. ; Cope L. Todd,MYX ; Reddy Srinivas ; Cliff Richard G., System for distributing clocks using a delay lock loop in a programmable logic circuit.
    상세보기
  8. Eto Satoshi,JPX ; Taguchi Masao,JPX ; Matsumiya Masato,JPX ; Nakamura Toshikazu,JPX ; Takita Masato,JPX ; Higashiho Mitsuhiro,JPX ; Koga Toru,JPX ; Kano Hideki,JPX ; Kitamoto Ayako,JPX ; Kawabata Kun, Variable delay circuit and semiconductor integrated circuit device.
    상세보기

이 특허를 인용한 특허 (75)

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  3. Lin, Feng, Capture clock generator using master and slave delay locked loops.
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  4. Lee, Seong-Hoon, Clock generating circuit with multiple modes of operation.
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  5. Lee,Seong Hoon, Clock generating circuit with multiple modes of operation.
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  7. Gomm, Tyler J., Clock synchronizing apparatus and method using frequency dependent variable delay.
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  8. Suzuki, Misao, DLL circuit capable of preventing malfunctioning causing locking in an antiphase state.
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  9. Sekiguchi, Yuji; Miki, Yoichiro, Data latch timing adjustment apparatus.
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  10. Gomm, Tyler J.; Bell, Debra, Delay line off-state control with power reduction.
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  14. Bae, Seung-Jun, Delay locked loop circuit, semiconductor device having the same and method of controlling the same.
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  17. Kim, Kang Yong; Choi, Dong Myung, Delay stage-interweaved analog DLL/PLL.
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  19. Gomm, Tyler J.; Alejano, Frank; Kirsch, Howard C., Delay-locked loop circuit and method using a ring oscillator and counter-based delay.
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  23. Baker, R. Jacob; Lin, Feng, Digital dual-loop DLL design using coarse and fine loops.
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  24. Fu,Wei; Balardeta,Joseph J., Distributed clock network using all-digital master-slave delay lock loops.
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  25. Drexler, Adrian J., Dual-phase delay-locked loop circuit and method.
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  67. Lin, Feng; Baker, R. Jacob, Phase splitter using digital delay locked loops.
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  68. Gomm, Tyler J.; Dirkes, Travis E.; Dermott, Ross E.; Loughmiller, Daniel R.; Smith, Scott E., Power reduction for delay locked loop circuits.
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  74. Lin, Feng, System and method of operation of DLL and PLL to provide tight locking with large range, and dynamic tracking of PVT variations using interleaved delay lines.
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  75. Lin, Feng, System and method to provide tight locking for DLL and PLL with large range, and dynamic tracking of PVT variations using interleaved delay lines.
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