초록 ▼

Disclosed herein is a process-tracking clock duty cycle integrator. Common mode feedback is used to set a common mode output voltage that varies with the voltage threshold of MOS elements that implement the circuit. In addition, a buffer is used to control the common mode input voltage to the differ

Disclosed herein is a process-tracking clock duty cycle integrator. Common mode feedback is used to set a common mode output voltage that varies with the voltage threshold of MOS elements that implement the circuit. In addition, a buffer is used to control the common mode input voltage to the differential amplifier circuit, and to vary the common mode input voltage with the voltage threshold.

대표청구항 ▼

Disclosed herein is a process-tracking clock duty cycle integrator. Common mode feedback is used to set a common mode output voltage that varies with the voltage threshold of MOS elements that implement the circuit. In addition, a buffer is used to control the common mode input voltage to the differ

Disclosed herein is a process-tracking clock duty cycle integrator. Common mode feedback is used to set a common mode output voltage that varies with the voltage threshold of MOS elements that implement the circuit. In addition, a buffer is used to control the common mode input voltage to the differential amplifier circuit, and to vary the common mode input voltage with the voltage threshold. nel transistor than the second n-channel transistor. 7. The integrated circuit of claim 4, wherein the first p-channel transistor is a wider gate width transistor than the second p-channel transistor. 8. The integrated circuit of claim 4, wherein the first n-channel transistor is a wider gate width transistor than the second n-channel transistor. 9. The integrated circuit of claim 1, wherein the leakage current offset circuit comprises a transistor, and wherein the adjustment circuit is operatively connected to a gate of the transistor. 10. The integrated circuit of claim 1, wherein the test processor unit is arranged to respond to an instruction. 11. The integrated circuit claim 1, wherein the test processor unit generates a binary control word. 12. The integrated circuit of claim 11, wherein the adjustment circuit is responsive to the binary control word. 13. A method for post-fabrication treatment of a delay locked loop, comprising: generating a delayed clock signal; comparing the delayed clock signal to an input clock signal; storing a voltage potential on a capacitor dependent on the comparing; generating a binary control word using a test processor unit; selectively adjusting an adjustment circuit responsive to the binary control word; and compensating a leakage current of the capacitor dependent on the selectively adjusting. 14. The method of claim 13, wherein compensating uses a leakage current offset circuit. 15. The method of claim 14, wherein the selectively adjusting uses the adjustment circuit to operatively control a gate of a transistor in the leakage current offset circuit. 16. The method of claim 13, wherein the selectively adjusting the adjustment circuit comprises: controlling a first current flow between a first voltage potential and an output of the adjustment circuit; and controlling a second current flow between a second voltage potential and the output of the adjustment circuit. 17. The method of claim 13, wherein the adjustment circuit comprises a first p-channel transistor and a first n-channel transistor connected in series. 18. The method of claim 17, the adjustment circuit further comprising: a second p-channel transistor connected in parallel with the first p-channel transistor; and a second n-channel transistor connected in parallel with the first n-channel transistor, wherein the first p-channel transistor and second p-channel transistor are in series with the first n-channel transistor and second n-channel transistor. 19. The method of claim 18, wherein the first p-channel transistor is a longer channel transistor than the second p-channel transistor. 20. The method of claim 18, wherein the first n-channel transistor is a longer channel transistor than the second n-channel transistor. 21. The method of claim 18, wherein the first p-channel transistor is a wider gate width transistor than the second p-channel transistor. 22. The method of claim 18, wherein the first n-channel transistor is a wider gate width transistor than the second n-channel transistor. 23. The method of claim 13, wherein the leakage current offset circuit comprises a transistor. 24. The method of claim 13, wherein the selectively adjusting comprises: using the test processor unit to adjust the adjustment circuit to one of a fixed number of possible settings. 25. An integrated circuit, comprising: means for generating a delayed clock signal; means for comparing the delayed clock signal to an input clock signal; means for storing a voltage potential dependent on the means for comparing; means for generating a binary control word; and means for adjusting the voltage potential dependent on the binary control word. or providing a data output signal, and a control node for receiving the control signal, an inverter having an input coupled to the output of the first pass gate and an output; and a correcting inverter stage having a first input coupled to the output of the inverter, and second and third inputs for receiving voting signals from adjacent error-correcting latch stages, and an output coupled to the output of the second pass gate. A full latch stage includes three interconnected partial latch stages. The full latch stage has a high degree of immunity from SEU events and from on-chip noise coupling. n response to the input signal having a voltage greater than the voltage threshold, and a PMOS drive circuit having a drive terminal coupled to the gate of the PMOS pull-up transistor and further coupled to the bias terminal through a balance switch to couple the body and gate terminals of the pull-up transistor during the input mode. 2. The I/O buffer of claim 1 wherein the pull-down transistor comprises an NMOS transistor. 3. The I/O buffer of claim 1 wherein the voltage threshold is approximately equal to the voltage of the first supply voltage. 4. The I/O buffer of claim 1 wherein the PMOS pull-up transistor is formed in an n-well. 5. An input/output (I/O)buffer coupled between first and second supply voltages for receiving an input signal during an input mode and for providing an output signal during an output mode, the I/O buffer comprising: a driver circuit having pull-up and pull-down transistors coupled in series and an I/O node disposed therebetween to receive the input signal, the pull up transistor having gate and body terminals; and a pull-up transistor bias circuit having a bias terminal coupled to the gate and body terminals of the pull-up transistor, a well pulling circuit having a first drive transistor coupled between the first supply voltage and the bias terminal to couple the bias terminal to the first supply voltage during the input mode in response to the input signal having a voltage less than a voltage threshold, the well pulling circuit further having a second drive transistor coupled between the bias terminal and the I/O node to couple the bias terminal to the I/O node in response to the input signal having a voltage greater than the voltage threshold, and a pull-up transistor drive circuit having a drive terminal coupled to the gate of the pull-up transistor and further coupled to the bias terminal through a balance switch to couple the body and gate terminals of the pull-up transistor during the input mode. 6. The I/O buffer of claim 5 wherein the pull-up transistor comprises a PMOS transistor. 7. The I/O buffer of claim 6 wherein the PMOS pull-up transistor is formed in an n-well. 8. The I/O buffer of claim 5 wherein the pull-down transistor comprises an NMOS transistor. 9. The I/O buffer of claim 5 wherein the voltage threshold is approximately equal to the voltage of the first supply voltage. 10. The I/O buffer of claim 5 wherein the well pulling circuit comprises: a pass gate having an input terminal coupled to the I/O node, and further having an output terminal and p- and n-gate terminals, the pass gate coupling a signal applied to the input terminal to the output terminal in response to receiving activation signals on the p- and n-gate terminals; a p-pass gate bias circuit having a p-gate activation terminal coupled to the p-gate terminal of the pass gate and an activation terminal coupled to the output terminal of the pass gate, and further having a second source activation terminal, the p-pass gate bias circuit providing an activation signal on the second source activation terminal responsive to signal provided on the output terminal of the pass gate; a well switch having a bias output coupled to the bias terminal, a first activation terminal coupled to the output terminal of the pass gate, a second activation terminal coupled to the second source activation terminal of the p-pass gate bias circuit, a first source terminal coupled to the first supply voltage and a second source terminal coupled to the I/O node, the well switch coupling the I/O node to the bias output responsive to an activation signal received on the second activation terminal and coupling the first voltage source to the bias output responsive to the output of the pass gate; and a first discharge path coupled to the first activation terminal and a second discharge path coupled to the n-gate terminal to discharge the respective nodes in response to the I/O buffer entering the output mode. 11. The I/O buffer