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A dual-loop digital delay locked loop (DLL) is provided. The DLL includes a coarse loop to produce a first delayed signal and provides a wide frequency lock range. The DLL further includes a fine loop connected to the coarse loop to produce a second delayed signal and provides a tight locking. This

A dual-loop digital delay locked loop (DLL) is provided. The DLL includes a coarse loop to produce a first delayed signal and provides a wide frequency lock range. The DLL further includes a fine loop connected to the coarse loop to produce a second delayed signal and provides a tight locking. This dual-loop architecture can provide robust operation and tight synchronization over a wide range of delay variations.

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1. A circuit comprising:a first delay line for applying a first delay to an input signal to produce a first delayed signal;a first phase detector connected to the first delay line for comparing the input signal and a feedback signal to produce first shifting signals;a first shift register connected

1. A circuit comprising:a first delay line for applying a first delay to an input signal to produce a first delayed signal;a first phase detector connected to the first delay line for comparing the input signal and a feedback signal to produce first shifting signals;a first shift register connected to the first phase detector for adjusting the first delay based on the first shifting signals, the first shift register including a number of register cells, each connecting to multiple delay cells of the first delay line;a second delay line connected to the first delay line for applying a second delay to the first delayed signal to produce a second delayed signal;a second phase detector connected to the second delay line for comparing the input signal and the feedback signal to produce second shifting signals; anda second shift register connected to the second phase detector for adjusting the second delay based on the second shifting signals. 2. The circuit of claim 1 further comprising a delay model connected to the second delay line for delaying the second delayed signal to produce the feedback signal. 3. The circuit of claim 1, wherein the first delay line includes a plurality of delay cells, each having identical delay elements. 4. The circuit of claim 3, wherein the second delay line includes a plurality of delay cells, each having a time delay smaller than a time delay of each of the delay cells of the first delay line. 5. The circuit of claim 3, wherein the first shift register includes a plurality of register cells, each connecting to multiple delay cells of the first delay line. 6. A circuit comprising:a coarse loop including:a first delay line including a plurality of delay cells of a first delay range for applying a first delay to an input signal to produce a first signal delayed from the input signal by a first time delay;a first phase detector connected to the first delay line for comparing the input signal and a feedback signal to produce first shifting signals; anda first shift register including a plurality of register cells, each connecting to multiple delay cells for adjusting the first delay based on the first shifting signals; anda fine loop including second delay range smaller than the first delay range, the fine loop connecting to the coarse loop for receiving the first signal to produce a second signal delayed from the input signal by a second time delay smaller than the first time delay. 7. The circuit of claim 6, wherein the fine loop includes:a second delay line connected to the first delay line for applying a second delay to the first signal;a second phase detector connected to the second delay line for comparing the input signal and the feedback signal to produce second shifting signals; anda second shift register connected to the second phase detector for adjusting the second delay based on the second shifting signals. 8. The circuit of claim 6, wherein the delay cells include a plurality of identical delay elements. 9. The circuit of claim 6, wherein each of the delay cells includes only NAND gates. 10. The circuit of claim 6 further comprising a delay model connected to the second delay line for delaying the second signal to produce the feedback signal. 11. A circuit comprising:a forward path including a coarse loop for delaying an input signal to produce a first signal having a first time delay from the input signal, and a fine loop connected to the coarse loop for delaying the first signal to produce a second signal having a second time delay from the input signal, the second time delay being smaller than the first time delay; anda feedback path connected to the forward path for delaying the second signal to produce a feedback signal, the coarse loop including:a coarse delay line including a plurality of delay cells for applying a coarse delay to the input signal to produce the first signal;a coarse phase detector connected to the coarse delay line for comparing the input and feedback signals to pr oduce coarse shifting signals; anda coarse shift register including a plurality of register cells, each connecting to multiple delay cells for adjusting the coarse delay based on the coarse shifting signals. 12. The circuit of claim 11, wherein the fine loop includes:a fine delay line connected to the coarse delay line for applying a fine delay smaller than the coarse delay to the first signal to produce the second signal;a fine phase detector connected to the fine delay line for comparing the input and feedback signals to produce fine shifting signals; anda fine shift register connected to the fine phase detector for adjusting the fine delay based on the fine shifting signals. 13. The circuit of claim 12, wherein the fine delay line includes a plurality of delay cells, each having a time delay smaller than a time delay of each of the delay cells of the coarse delay line. 14. The circuit of claim 11, wherein each of the delay cells of the coarse delay line includes identical delay elements. 15. The circuit of claim 14, wherein the identical delay elements are NAND gates. 16. A phase generator comprising;an input node to receive an input signal;a plurality of delay lines connected in series, each of the delay lines including a plurality of delay cells, each of the delay cells including identical delay elements, each of the delay lines including an output to produce an output signal, wherein one of the delay line is connected to the input node to receive the input signal; anda shift register including a plurality of register cells, each connecting to two delay cells to control the delay lines to make the output signal of each of the delay lines a multiple of N degrees out of phase with the input signal. 17. The phase generator of claim 16, wherein the identical delay elements are NAND gates. 18. The phase generator of claim 16, wherein the output signal of each of the delay lines is 90 degrees out of phase with the input signal. 19. The phase generator of claim 16 further comprising a phase detector connected to the shift register for providing control signals to the shift register. 20. A phase generator comprising:an input node to receive an input signal;a plurality of delay lines connected in series, each of the delay lines including a coarse loop connected to a fine loop, the coarse loop including a plurality of delay cells, each of the delay cells including identical delay elements, the fine loop of a previous delay line being connected to the coarse loop of the next delay line, and each of the delay lines including an output to produce an output signal, wherein one of the delay lines is connected to the input node to receive the input signal; anda shift register including a plurality of register cells, each of the register cells being connected to two delay cells to control the delay lines to make the output of each of the delay lines a multiple of N degrees out of phase with the input signal. 21. The phase generator of claim 20, wherein the fine loop includes a plurality of delay cells, each having a time delay smaller than a time delay of each of the delay cells of the coarse loop. 22. The phase generator of claim 20, wherein the identical delay elements are NAND gates. 23. The phase generator of claim 20, wherein the output signal of each of the delay lines is 90 degrees out of phase with the input signal. 24. The phase generator of claim 20 further comprising a phase detector connected to the shift register for providing control signals to the shift register. 25. A memory device comprising:a plurality of memory cells;an output circuit connected to the memory cells; anda delay circuit connected to the output circuit for controlling data transfer between the memory cells and the output circuit, the delay circuit including:a coarse loop including:a first delay line including a plurality of delay cells of a first delay range for applying a first delay to an input signal to produce a first signal delayed from the input signa l by a first time delay;a first phase detector connected to the first delay line for comparing the input signal and a feedback signal to produce first shifting signals; anda first shift register including a plurality of register cells, each connecting to multiple delay cells for adjusting the first delay based on the first shifting signals; anda fine loop including second delay range smaller than the first delay range, the fine loop connecting to the coarse loop for receiving the first signal to produce a second signal delayed from the input signal by a second time delay smaller than the first time delay. 26. The memory device of claim 25, wherein the fine loop includes:a second delay line connected to the first delay line for applying a second delay to the first signal;a second phase detector connected to the second delay line for comparing the input signal and the feedback signal to produce second shifting signals; anda second shift register connected to the second phase detector for adjusting the second delay based on the second shifting signals. 27. The memory device of claim 25, wherein the delay cells include a plurality of identical delay elements. 28. The memory device of claim 25, wherein each of the delay cells includes only NAND gates. 29. The memory device of claim 25 further comprising a delay model connected to the second delay line for delaying the second signal to produce the feedback signal. 30. A system comprising:a processor; anda memory device connected to the processor, the memory device including:a plurality of memory cells;an output circuit connected to the memory cells;a delay circuit connected to the output circuit for controlling data transfer between the memory cells and the output circuit, the delay circuit including:a first delay line connected to the first delay line for applying a first delay to an input signal to produce a first delayed signal;a first phase detector connected to the first delay line for comparing the input signal and a feedback signal to produce first shifting signals;a first shift register connected to the first phase detector for adjusting the first delay based on the first shifting signals, the first shift register including a number of register cells, each connecting to multiple delay cells of the first delay line;a second delay line connected to the first delay line for applying a second delay to the first delayed signal to produce a second delayed signal;a second phase detector connected to the second delay line for comparing the input signal and the feedback signal to produce second shifting signals; anda second shift register connected to the second phase detector for adjusting the second delay based on the second shifting signals. 31. The system of claim 30 further comprising a delay model connected to the second delay line for delaying the second delayed signal to produce the feedback signal. 32. The system of claim 30, wherein the first delay line includes a plurality of delay cells, each having identical delay elements. 33. The system of claim 32, wherein the second delay line includes a plurality of delay cells, each having a time delay smaller than a time delay of each of the delay cells of the first delay line. 34. The system of claim 32, wherein the first shift register includes a plurality of register cells, each connecting to multiple delay cells of the first delay line. 35. A method comprising:applying a first delay, using a delay line, to an input signal to produce a first delayed signal;comparing the input signal and a feedback signal to produce first shifting signals;adjusting the first delay based on the first shifting signals wherein adjusting the first delay is performed by a shift register, the shift register including a number of register cells, each connecting to multiple delay cells of the delay line;applying a second delay to the first delayed signal to produce a second delayed signal;comparing the input signal and the feedback signal to produce sec ond shifting signals; andadjusting the second delay based on the second shifting signals. 36. The method of claim 35 further comprising:delaying the second delayed signal to produce the feedback signal. 37. The method of claim 35, wherein the second delay is smaller than the first delay. 38. The method of claim 35, wherein adjusting the second delay is performed until the input and feedback signal are synchronized. 39. A method comprising:applying a first delay, using a delay line, to an input signal using a coarse loop including a coarse range to produce a first signal delayed from the input signal by a first time delay;comparing the input signal and a feedback signal to produce first shifting signals;adjusting the first delay based on the first shifting signals wherein adjusting the first delay is performed by a shift register, the shift register including a number of register cells, each connecting to multiple delay cells of the delay line; andproducing a second signal delayed using a fine loop including a fine delay range smaller than the coarse delay range to produce, the second signal being delayed from the input signal by a second time delay smaller than the first time delay. 40. The method of claim 39, wherein producing a second signal includes:applying a second delay to the first signal;comparing the input signal and the feedback signal to produce second shifting signals; andadjusting the second delay based on the second shifting signals. 41. The method of claim 40 further comprising:delaying the second signal to produce the feedback signal. 42. A method for synchronizing signals, the method comprising:applying a first amount of delay, using a delay line, to an input signal using a plurality of delay cells of a coarse loop to produce a first delayed signal, each of the delay cell having identical delay elements;applying a second amount of delay to the first delayed signal at a fine loop to produce an output signal;delaying the output signal to produce a feedback signal;comparing the feedback signal and the input signal; andadjusting the first amount of delay and the second amount of delay wherein adjusting the first amount of delay is performed by a shift register, the shift register including a number of register cells, each connecting to multiple delay cells of the delay line. 43. The method of claim 42, wherein adjusting the second amount of delay is performed by a another shift register. 44. The method of claim 42, wherein applying the first amount of delay including applying an amount of delay in a first delay range. 45. The method of claim 42, wherein applying the second amount of delay including applying an amount of delay in a second delay range smaller than the first delay range. 46. A method of operating a memory device comprising:accessing a memory cell to obtain a data signal;propagating the data signal from the memory cell to an output circuit;applying a delayed signal to activate the output circuit, wherein applying a delayed signal includes propagating a clock signal through a delay circuit including a coarse loop and a fine loop controlled by a shift register, the coarse loop having a first delay range, the fine loop having a second delay range smaller than the first delay range, the coarse loop including a plurality of delay cells, each having identical delay elements, the shift register including a plurality of register cells, each connecting to two delay cells;producing a strobe signal from the delayed signal;propagating the data signal from the output circuit to an output pad; andadjusting the delayed signal at the delay circuit to synchronize the strobe signal and the data signal at the output pad. 47. A method of synchronizing signals, the method comprising:initiating a read operation;reading a memory cell to obtain a data signal at an output circuit;providing a delayed signal to the output circuit to using a delay circuit including a coarse loop and a fine loop controlled by a shift register, th e coarse loop having a first delay range, the fine loop having a second delay range smaller than the first delay range, the coarse loop including a plurality of delay cells, each having identical delay elements, the shift register including a plurality of register cells, each connecting to two delay cells; andproducing a strobe signal synchronized with the data signal using the delay circuit.