초록 ▼

A delay circuit is to produce a delay timing which is larger than one cycle time of a reference clock while the resolution of which is smaller than the one cycle time of the reference clock. The delay circuit includes a coarse delay circuit for producing a borrow signal having a delay time which is

A delay circuit is to produce a delay timing which is larger than one cycle time of a reference clock while the resolution of which is smaller than the one cycle time of the reference clock. The delay circuit includes a coarse delay circuit for producing a borrow signal having a delay time which is an integer multiple of one cycle time of a clock signal supplied thereto, a divider for dividing the frequency of the reference clock to produce the clock signal, a flip-flop circuit for delaying an incoming signal by one cycle time of the reference clock, a re-timing circuit for receiving an output signal from the flip-flop circuit and producing a coarse delay signal in synchronism with the reference clock, a decoder for receiving the borrow signal from the coarse delay circuit and selectively providing the borrow signal to either the flip-flop circuit or the re-timing circuit, and a fine delay circuit for adding a fine delay time which is smaller than the one cycle time of the reference clock to a coarse delay signal from the re-timing circuit.

대표청구항 ▼

[ What is claimed is:] [1.] A delay circuit for producing a delay timing which is longer than one cycle time of a reference clock while resolution of the delay timing is smaller than said one cycle time of said reference clock, comprising:a coarse delay circuit for producing a borrow signal having a

[ What is claimed is:] [1.] A delay circuit for producing a delay timing which is longer than one cycle time of a reference clock while resolution of the delay timing is smaller than said one cycle time of said reference clock, comprising:a coarse delay circuit for producing a borrow signal having a delay time which is an integer multiple of one cycle time of a clock signal supplied thereto;a divider for dividing a frequency of said reference clock to produce said clock signal supplied to said coarse delay circuit;a flip-flop circuit which is supplied with said reference clock for delaying an incoming signal by one time period of said reference clock;a re-timing circuit for receiving an output signal from said flip-flop circuit and producing a coarse delay signal in synchronism with said reference clock;a decoder for receiving said borrow signal from said coarse delay circuit and selectively providing said borrow signal to either said flip-flop circuit or said re-timing circuit; anda fine delay circuit for adding a fine delay time which is smaller than said one cycle time of said reference clock to said coarse delay signal from said re-timing circuit.