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Method of forming a via hole through a glass wafer 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/302
  • H01L-021/02
출원번호 US-0681217 (2003-10-09)
우선권정보 KR-10-2002-0070121(2002-11-12)
발명자 / 주소
  • Lee,Moon chul
  • Choi,Hyung
  • Jung,Kyu dong
  • Jang,Mi
  • Hong,Seog woo
  • Chung,Seok whan
  • Jun,Chan bong
  • Kang,Seok jin
출원인 / 주소
  • Samsung Electronics Co., Ltd.
대리인 / 주소
    Lee &
인용정보 피인용 횟수 : 51  인용 특허 : 7

초록

A method of forming a via hole through a glass wafer includes depositing a material layer on an outer surface of the glass wafer, the material layer having a selection ratio higher than that of the glass wafer, forming a via-patterned portion on one side of the material layer, performing a first etc

대표청구항

What is claimed is: 1. A method of forming a via hole through a glass wafer, comprising: depositing a first material layer on front and rear surfaces of the glass wafer; depositing a second material layer on the first material layer; forming a via pattern in the second material layer; performing a

이 특허에 인용된 특허 (7)

  1. Nader Najafi ; Yafan Zhang ; Terry Hull, Electrical feedthrough structures for micromachined devices and methods of fabricating the same.
  2. Umetsu, Kazushige, Electro-optical device and method of manufacture thereof, and electronic instrument.
  3. Corso, Thomas N., Fabrication of a microchip-based electrospray device.
  4. Christopher P Fell GB; Kevin Townsend GB; Ian Sturland GB, Method of manufacturing a vibrating structure gyroscope.
  5. Weigert, Martin, Process for the production of a glass article having at least one recess.
  6. Wei Liu ; Yiqiong Wang ; Maocheng Li ; Anisul Khan ; Shaoher Pan ; Dragan Podlesnik, Silicon trench etch using silicon-containing precursors to reduce or avoid mask erosion.
  7. Shimizu, Nobuo; Yotsuya, Shinichi; Yamashita, Hideto; Murata, Masami; Akiyama, Koichi, System and method for providing a substrate having micro-lenses.

이 특허를 인용한 특허 (51)

  1. Sulfridge, Marc, Conductive interconnect structures and formation methods using supercritical fluids.
  2. Sulfridge, Marc, Conductive interconnect structures and formation methods using supercritical fluids.
  3. Sulfridge, Marc, Conductive interconnect structures and formation methods using supercritical fluids.
  4. Janzen, Jeffery W.; Chaine, Michael; Kirby, Kyle K.; Hiatt, William M., Disabling electrical connections using pass-through 3D interconnects and associated systems and methods.
  5. Janzen, Jeffery W.; Chaine, Michael; Kirby, Kyle K.; Hiatt, William M., Disabling electrical connections using pass-through 3D interconnects and associated systems and methods.
  6. Janzen, Jeffery W.; Chaine, Michael; Kirby, Kyle K.; Hiatt, William M., Disabling electrical connections using pass-through 3D interconnects and associated systems and methods.
  7. Janzen, Jeffery W.; Chaine, Michael; Kirby, Kyle K.; Hiatt, William M., Disabling electrical connections using pass-through 3D interconnects and associated systems and methods.
  8. Janzen, Jeffery W.; Slifer, legal representative, Russell D.; Chaine, Michael; Kirby, Kyle K.; Hiatt, William M., Disabling electrical connections using pass-through 3D interconnects and associated systems and methods.
  9. Boon, Suan Jeung; Chia, Yong Poo; Eng, Meow Koon, Interconnects for packaged semiconductor devices and methods for manufacturing such devices.
  10. Boon, Suan Jeung; Chia, Yong Poo; Eng, Meow Koon, Interconnects for packaged semiconductor devices and methods for manufacturing such devices.
  11. Suan Jeung, Boon; Yong Poo, Chia; Meow Koon, Eng, Interconnects for packaged semiconductor devices and methods for manufacturing such devices.
  12. Koelling, Fred, Method for creating through-connected vias and conductors on a substrate.
  13. Haque, Razi-ul; Wise, Kensall, Method of embedding material in a glass substrate.
  14. Chong, Chin Hui; Lee, Choon Kuan, Method of manufacturing an interposer.
  15. Kirby, Kyle K., Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods.
  16. Kirby, Kyle K., Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods.
  17. Sulfridge, Marc, Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods.
  18. Sulfridge, Marc, Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods.
  19. Sulfridge, Marc, Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods.
  20. Oliver,Steven D.; Kirby,Kyle K.; Hiatt,William M., Methods for forming interconnects in vias and microelectronic workpieces including such interconnects.
  21. Burket, Robert Carl; Goers, Uta-Barbara; Owusu, Samuel Odei; Petriwsky, Tammy Lynn, Methods for forming vias in glass substrates.
  22. Burket, Robert Carl; Goers, Uta-Barbara; Owusu, Samuel Odei; Petriwsky, Tammy Lynn, Methods for forming vias in glass substrates.
  23. Rigg,Sidney B.; Watkins,Charles M.; Kirby,Kyle K.; Benson,Peter A.; Akram,Salman, Methods for forming vias in microelectronic devices, and methods for packaging microelectronic devices.
  24. Hiatt, William M.; Kirby, Kyle K., Microelectronic devices and methods for filing vias in microelectronic devices.
  25. Hiatt, William M.; Kirby, Kyle K., Microelectronic devices and methods for filling vias in microelectronic devices.
  26. Kirby, Kyle K.; Akram, Salman; Hembree, David R.; Rigg, Sidney B.; Farnworth, Warren M.; Hiatt, William M., Microelectronic devices and methods for forming interconnects in microelectronic devices.
  27. Kirby, Kyle K.; Akram, Salman; Hembree, David R.; Rigg, Sidney B.; Farnworth, Warren M.; Hiatt, William M., Microelectronic devices and methods for forming interconnects in microelectronic devices.
  28. Clark, Douglas; Oliver, Steven D.; Kirby, Kyle K.; Dando, Ross S., Microelectronic workpieces and methods and systems for forming interconnects in microelectronic workpieces.
  29. Rigg, Sidney B.; Watkins, Charles M.; Kirby, Kyle K.; Benson, Peter A.; Akram, Salman, Microelectronics devices, having vias, and packaged microelectronic devices having vias.
  30. Lee, Teck Kheng; Lim, Andrew Chong Pei, Microfeature workpiece substrates having through-substrate vias, and associated methods of formation.
  31. Hiatt, William M.; Dando, Ross S., Microfeature workpieces and methods for forming interconnects in microfeature workpieces.
  32. Borthakur, Swarnal, Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and associated systems and methods.
  33. Borthakur, Swarnal, Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and associated systems and methods.
  34. Borthakur, Swarnal, Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and associated systems and methods.
  35. Tuttle, Mark E., Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods.
  36. Tuttle, Mark E., Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods.
  37. Lee, Teck Kheng, Partitioned through-layer via and associated systems and methods.
  38. Lee, Teck Kheng, Partitioned through-layer via and associated systems and methods.
  39. Lee, Teck Kheng, Partitioned through-layer via and associated systems and methods.
  40. Pratt, David S.; Kirby, Kyle K.; Ray, Dewali, Pass-through 3D interconnect for microelectronic dies and associated systems and methods.
  41. Pratt, David S.; Kirby, Kyle K.; Ray, Dewali, Pass-through interconnect structure for microelectronic dies and associated systems and methods.
  42. Chong,Chin Hui; Lee,Choon Kuan, Slanted vias for electrical circuits on circuit boards and other substrates.
  43. Hooper, Andy; Finn, Daragh; Webb, Tim; Sheehan, Lynn; Pettigrew, Kenneth; Tai, Yu Chong, Substrate containing aperture and methods of forming the same.
  44. Watkins, Charles M.; Hiatt, William M., System and methods for forming apertures in microfeature workpieces.
  45. Watkins, Charles M.; Hiatt, William M., Systems and methods for forming apertures in microfeature workpieces.
  46. Watkins, Charles M.; Hiatt, William M., Systems and methods for forming apertures in microfeature workpieces.
  47. Watkins, Charles M.; Hiatt, William M., Systems and methods for forming apertures in microfeature workpieces.
  48. Watkins, Charles M.; Hiatt, William M., Systems and methods for forming apertures in microfeature workpieces.
  49. Akram, Salman; Watkins, Charles M.; Hiatt, William M.; Hembree, David R.; Wark, James M.; Farnworth, Warren M.; Tuttle, Mark E.; Rigg, Sidney B.; Oliver, Steven D.; Kirby, Kyle K.; Wood, Alan G.; Velicky, Lu, Through-wafer interconnects for photoimager and memory wafers.
  50. Akram, Salman; Watkins, Charles M.; Hiatt, William M.; Hembree, David R.; Wark, James M.; Farnworth, Warren M.; Tuttle, Mark E.; Rigg, Sidney B.; Oliver, Steven D.; Kirby, Kyle K.; Wood, Alan G.; Velicky, Lu, Through-wafer interconnects for photoimager and memory wafers.
  51. Akram, Salman; Watkins, Charles M.; Hiatt, William M.; Hembree, David R.; Wark, James M.; Farnworth, Warren M.; Tuttle, Mark E.; Rigg, Sidney B.; Oliver, Steven D.; Kirby, Kyle K.; Wood, Alan G.; Velicky, Lu, Through-wafer interconnects for photoimager and memory wafers.
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