The present invention discloses a via-hole etching method related to semiconductor manufacturing field, and the method overcomes the defects of an uncontrollable end point of a via-hole and an unfavorable profile-angle in a conventional via-hole etching method. The via-hole etching method includes:
The present invention discloses a via-hole etching method related to semiconductor manufacturing field, and the method overcomes the defects of an uncontrollable end point of a via-hole and an unfavorable profile-angle in a conventional via-hole etching method. The via-hole etching method includes: forming a structure for via-hole etching, includes: a low-temperature poly-silicon layer, a gate insulating layer, a gate metal layer and an interlayer insulating layer, which are sequentially formed on a substrate; forming a mask layer comprising a via-hole masking pattern on the structure for via-hole etching; by using a first etching process, etching the structure for via-hole etching to a first thickness of the gate insulating layer; by using a second etching process, etching the structure for via-hole etching to etch away the remaining thickness of the gate insulating layer, and uncovering the low-temperature poly-silicon layer; removing the mask layer to form a via-hole structure.
대표청구항▼
1. A via-hole etching method, comprising: forming a structure for via-hole etching, comprising a low-temperature poly-silicon layer, a gate insulating layer, a gate metal layer and an interlayer insulating layer, which are sequentially formed on a substrate;forming a mask layer comprising a via-hole
1. A via-hole etching method, comprising: forming a structure for via-hole etching, comprising a low-temperature poly-silicon layer, a gate insulating layer, a gate metal layer and an interlayer insulating layer, which are sequentially formed on a substrate;forming a mask layer comprising a via-hole masking pattern on the structure for via-hole etching;by using a first etching process, etching the structure for via-hole etching to a first thickness of the gate insulating layer;by using a second etching process, etching the structure for via-hole etching to etch away a remaining thickness of the gate insulating layer uncovering the low-temperature poly-silicon layer and ending the second etching process so as to retain the low-temperature poly-silicon layer that is uncovered; andremoving the mask layer to form a via-hole structure;wherein the second etching process is dry etching with an organic etching gas, which is a mixed gas including CF4, hydrogen (H2), C4F8, Ar and O2. 2. The via-hole etching method according to claim 1, wherein the first etching process is dry etching. 3. The via-hole etching method according to claim 1, wherein for the first and second etching processes, an etching-chamber pressure is between 0 and 20 mtorr, and an etching power is not less than 5000 W. 4. The via-hole etching method according to claim 1, wherein a first thickness of the gate insulating layer is 700˜1400 Å. 5. The via-hole etching method according to claim 1, wherein a material of the gate insulating layer is any one or more materials from silicon nitride, silicon oxide and silicon carbide. 6. The via-hole etching method according to claim 1, wherein the formed via-hole structure has a profile-angle of 55°˜75°. 7. The via-hole etching method according to claim 2, wherein for the first and second etching processes, an etching-chamber pressure is between 0 and 20 mtorr, and an etching power is not less than 5000 W. 8. The via-hole etching method according to claim 2, wherein a first thickness of the gate insulating layer is 700˜1400 Å. 9. The via-hole etching method according to claim 2, wherein a material of the gate insulating layer is any one or more materials from silicon nitride, silicon oxide and silicon carbide. 10. The via-hole etching method according to claim 2, wherein the formed via-hole structure has a profile-angle of 55°˜75°. 11. The via-hole etching method according to claim 3, wherein a first thickness of the gate insulating layer is 700˜1400 Å. 12. The via-hole etching method according to claim 3, wherein a material of the gate insulating layer is any one or more materials from silicon nitride, silicon oxide and silicon carbide. 13. The via-hole etching method according to claim 3, wherein the formed via-hole structure has a profile-angle of 55°˜75°. 14. The via-hole etching method according to claim 4, wherein a material of the gate insulating layer is any one or more materials from silicon nitride, silicon oxide and silicon carbide. 15. The via-hole etching method according to claim 4, wherein the formed via-hole structure has a profile-angle of 55°˜75°. 16. The via-hole etching method according to claim 5, wherein the formed via-hole structure has a profile-angle of 55°˜75°.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (2)
Liu Meng-Chang,TWX ; Cheng Chao-Bao,TWX ; Hsu Kuo-Chin,TWX, Integrated method of damascene and borderless via process.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.