IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0308776
(2006-05-03)
|
등록번호 |
US-7323934
(2008-01-29)
|
우선권정보 |
TW-95103385 A(2006-01-27) |
발명자
/ 주소 |
|
출원인 / 주소 |
- Novatek Microelectronics Corp.
|
대리인 / 주소 |
|
인용정보 |
피인용 횟수 :
10 인용 특허 :
4 |
초록
▼
An operational transconductance amplifier (OTA) includes a first, a second and a third differential units, a voltage-to-current converting unit and a current subtraction device. The first and the second differential units receive a differential input voltage and the voltage-to-current converting uni
An operational transconductance amplifier (OTA) includes a first, a second and a third differential units, a voltage-to-current converting unit and a current subtraction device. The first and the second differential units receive a differential input voltage and the voltage-to-current converting unit converts it into an output current. The OTA adopts a replica scheme, that is, by copying the first differential unit to generate a third differential unit and then performs a subtraction between the first output current from the first differential unit and the second output current from the third differential unit in order to eliminate the static current component in the output current. In addition, since the first and the third differential units have the same layout, the output current will not vary with the channel length modulation of transistors, and the static current component in the output current can be eliminated completely.
대표청구항
▼
What is claimed is: 1. An operational transconductance amplifier (OTA) for receiving a differential input voltage and outputting an output current, wherein the differential input voltage comprises a first input voltage and a second input voltage; the OTA comprising: a first current source, a second
What is claimed is: 1. An operational transconductance amplifier (OTA) for receiving a differential input voltage and outputting an output current, wherein the differential input voltage comprises a first input voltage and a second input voltage; the OTA comprising: a first current source, a second current source and a third current source for providing a first source bias current, a second source bias current and a third source bias current, respectively, wherein the first source bias current and the third source bias current are the same; a first current sink, a second current sink and a third current sink for providing a first sink bias current, a second sink bias current and a third sink bias current, respectively, wherein the first sink bias current and the third sink bias current are the same; a first differential unit biased by the first source bias current and the first sink bias current for receiving the second input voltage; a second differential unit biased by the second source bias current and the second sink bias current for receiving the first input voltage; a third differential unit biased by the third source bias current and the third sink bias current for receiving the second input voltage, wherein the third differential unit is coupled to the first differential unit and the third differential unit has the substantially same configuration as the first differential unit; a voltage-to-current converting unit coupled between the first and the second differential units for providing a conversion current according to the voltage difference between the first input voltage and the second input voltage; and a current subtraction device for outputting the output current obtained from a subtraction between a first output current multiplied by a factor and a second output current multiplied by the factor, wherein the first output current is provided by the first differential unit according to the first source bias current, the first sink bias current and the conversion current, and the second output current is provided by the third differential unit according to the third source bias current and the third sink bias current. 2. The OTA as recited in claim 1, wherein the voltage-to-current converting unit is an element possessing a resistance. 3. The OTA as recited in claim 1, wherein the first differential unit comprises a first terminal, a second terminal, a first differential transistor and a first shunt transistor, wherein a gate terminal of the first differential transistor receives the second input voltage, a first source/drain terminal of the first differential transistor and a first source/drain terminal of the first shunt transistor are coupled to the first terminal of the first differential unit to receive the first source bias current, a second source/drain terminal of the first shunt transistor is grounded and a second source/drain terminal of the first differential transistor and a gate terminal of the first shunt transistor are coupled to the second terminal of the first differential unit to output the first sink bias current and a voltage corresponding to the first output current. 4. The OTA as recited in claim 3, wherein the second differential unit comprises a first terminal, a second terminal, a second differential transistor and a second shunt transistor, wherein a gate terminal of the second differential transistor receives the first input voltage, a first source/drain terminal of the second differential transistor and a first source/drain terminal of the second shunt transistor are coupled to the first terminal of the second differential unit to receive the second source bias current, a second source/drain terminal of the second shunt transistor is grounded and a second source/drain terminal of the second differential transistor and a gate terminal of the second shunt transistor are coupled to the second terminal of the second differential unit to output the second sink bias current. 5. The OTA as recited in claim 4, wherein the third differential unit comprises a first terminal, a second terminal, a third differential transistor and a third shunt transistor, wherein a gate terminal of the third differential transistor receives the second input voltage, a first source/drain terminal of the third differential transistor and a first source/drain terminal of the third shunt transistor are coupled to the first terminal of the third differential unit to receive the third source bias current, a second source/drain terminal of the third shunt transistor is grounded and a second source/drain terminal of the third differential transistor and a gate terminal of the third shunt transistor are coupled to the second terminal of the third differential unit to output the third sink bias current and a voltage corresponding to the second output current. 6. The OTA as recited in claim 5, wherein the first, the second and the third differential transistors are P-channel metal-oxide-semiconductor (MOS) transistors, while the first, the second and the third shunt transistors are N-channel MOS transistors. 7. The OTA as recited in claim 5, wherein the current subtraction device comprises: a first conversion transistor, wherein a gate terminal of the first conversion transistor is coupled to the second terminal of the first differential unit and a second source/drain terminal of the first conversion transistor is grounded, the first output current multiplied by the factor being output at the first source/drain terminal of the first conversion transistor according to the voltage at the second terminal of the first differential unit; a second conversion transistor, wherein a gate terminal of the second conversion transistor is coupled to the second terminal of the third differential unit and a second source/drain terminal of the second conversion transistor is grounded, the second output current multiplied by the factor being output at the first source/drain terminal of the second conversion transistor according to the voltage at the second terminal of the third differential unit; and a current mirror coupled between the first source/drain terminal of the first conversion transistor and the first source/drain terminal of the second conversion transistor for copying one of the first output current multiplied by the factor and the second output current multiplied by the factor onto the other one to perform a subtraction between the first output current multiplied by the factor and the second output current multiplied by the factor. 8. The OTA as recited in claim 7, wherein an aspect ratio of the first conversion transistor is proportional to an aspect ratio of the first shunt transistor in the factor, while an aspect ratio of the second conversion transistor is proportional to an aspect ratio of the third shunt transistor in the same factor. 9. The OTA as recited in claim 7, wherein the factor is one. 10. The OTA as recited in claim 8, wherein the first and the second conversion transistors are N-channel MOS transistors. 11. An operational transconductance amplifier (OTA) for receiving a differential input voltage and outputting an output current, wherein the differential input voltage comprises a first input voltage and a second input voltage; the OTA comprising: a differential pair unit, comprising: a first differential unit for receiving the first input voltage; a second differential unit for receiving the second input voltage; and a voltage-to-current converting unit coupled between the first and the second differential units for providing a conversion current according to the voltage difference between the first input voltage and the second input voltage, wherein the first differential unit provides a first output current according to the conversion current; a current copy unit having the substantially same configuration as the first differential unit for receiving the second input voltage and outputting a second output current; and a current subtraction device for outputting the output current obtain from a subtraction the first output current multiplied by a factor and the second output current multiplied by the factor. 12. The OTA as recited in claim 11, wherein the voltage-to-current converting unit is an element possessing a resistance. 13. The OTA as recited in claim 11, wherein the first differential unit comprises a first terminal, a second terminal, a first differential transistor and a first shunt transistor, wherein a gate terminal of the first differential transistor receives the second input voltage, a first source/drain terminal of the first differential transistor and a first source/drain terminal of the first shunt transistor are coupled to the first terminal of the first differential unit to receive a first source bias current, a second source/drain terminal of the first shunt transistor is grounded and a second source/drain terminal of the first differential transistor and a gate terminal of the first shunt transistor are coupled to the second terminal of the first differential unit to output a first sink bias current and a voltage corresponding to the first output current. 14. The OTA as recited in claim 13, wherein the second differential unit comprises a first terminal, a second terminal, a second differential transistor and a second shunt transistor, wherein a gate terminal of the second differential transistor receives the first input voltage, a first source/drain terminal of the second differential transistor and a first source/drain terminal of the second shunt transistor are coupled to the first terminal of the second differential unit to receive a second source bias current, a second source/drain terminal of the second shunt transistor is grounded and a second source/drain terminal of the second differential transistor and a gate terminal of the second shunt transistor are coupled to the second terminal of the second differential unit to output a second sink bias current. 15. The OTA as recited in claim 14, wherein the current copy unit comprises a first terminal, a second terminal, a third differential transistor and a third shunt transistor, wherein a gate terminal of the third differential transistor receives the second input voltage, a the first source/drain terminal of the third differential transistor and a first source/drain terminal of the third shunt transistor are coupled to the first terminal of the current copy unit to receive a third source bias current, a second source/drain terminal of the third shunt transistor is grounded and a second source/drain terminal of the third differential transistor and a gate terminal of the third shunt transistor are coupled to the second terminal of the current copy unit to output a third sink bias current and a voltage corresponding to the second output current. 16. The OTA as recited in claim 15, wherein the first, the second and the third differential transistors are P-channel metal-oxide-semiconductor (MOS) transistors, while the first, the second and the third shunt transistors are N-channel MOS transistors. 17. The OTA as recited in claim 15, wherein the current subtraction device comprises: a first conversion transistor, wherein a gate terminal of the first conversion transistor is coupled to the second terminal of the first differential unit and a second source/drain terminal of the first conversion transistor is grounded, the first output current multiplied by the factor being output at the first source/drain terminal of the first conversion transistor according to the voltage at the second terminal of the first differential unit; a second conversion transistor, wherein a gate terminal of the second conversion transistor is coupled to the second terminal of the current copy unit and a second source/drain terminal of the second conversion transistor is grounded, the second output current multiplied by the factor being output at the first source/drain terminal of the second conversion transistor according to the voltage at the second terminal of the current copy unit; and a current mirror, coupled between the first source/drain terminal of the first conversion transistor and the first source/drain terminal of the second conversion transistor for copying one of the first output current multiplied by the factor and the second output current multiplied by the factor onto the other one to perform a subtraction between the first output current multiplied by the factor and the second output current multiplied by the factor. 18. The OTA as recited in claim 17, wherein an aspect ratio of the first conversion transistor is proportional to an aspect ratio of the first shunt transistor in the factor, while an aspect ratio of the second conversion transistor is proportional to an aspect ratio of the third shunt transistor in the same factor. 19. The OTA as recited in claim 17, wherein the factor is one. 20. The OTA as recited in claim 18, wherein the first and the second conversion transistors are N-channel MOS transistors.
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