초록 ▼

The first source and drain regions are formed in an upper surface of a SiGe substrate. The first source and drain regions containing an N type impurity. Vacancy concentration in the first source and drain regions are reduced in order to reduce diffusion of the N type impurity contained in the first

The first source and drain regions are formed in an upper surface of a SiGe substrate. The first source and drain regions containing an N type impurity. Vacancy concentration in the first source and drain regions are reduced in order to reduce diffusion of the N type impurity contained in the first source and drain regions. The vacancy concentration is reduced by an interstitial element or a vacancy-trapping element in the first source and drain regions. The interstitial element or the vacancy-trapping element is provided by ion-implantation.

대표청구항 ▼

The invention claimed is: 1. A semiconductor device comprising: a relaxed SiGe-based substrate; a tensile biaxially strained Si cap layer formed on the relaxed SiGe-based substrate; a gate electrode formed on the relaxed SiGe-based substrate with a gate oxide formed on the Si cap layer; source and

The invention claimed is: 1. A semiconductor device comprising: a relaxed SiGe-based substrate; a tensile biaxially strained Si cap layer formed on the relaxed SiGe-based substrate; a gate electrode formed on the relaxed SiGe-based substrate with a gate oxide formed on the Si cap layer; source and drain extension regions formed in an upper surface of the SiGe substrate and containing an N type impurity; and a low vacancy region that overlap the source and drain extension regions and containing an interstitial element or a vacancy-trapping element, wherein an implant profile of the interstitial element or the vacancy-trapping element fully contains an N type impurity profile, whereby diffusion retardation is maximized. 2. The semiconductor device of claim 1, wherein the interstitial element is Si or O and the vacancy-trapping element is F, N, Xe, Ar, He, Kr or a noble gas element. 3. The semiconductor device of claim 1, wherein each of the interstitial element or the vacancy-trapping element is ion-implanted. 4. The semiconductor device of claim 1, wherein the semiconductor device is an N type device. 5. The semiconductor device of claim 1, wherein the N type impurity is ion-implanted in a self-aligned manner. 6. The semiconductor device of claim 1, wherein the vacancy-trapping element forms vacancy-based clusters. 7. A semiconductor device comprising: a relaxed SiGe-based substrate; a tensile biaxially strained Si cap layer formed on the relaxed SiGe-based substrate and which matches a lattice of the relaxed SiGe-based substrate; a gate electrode formed on the SiGe-based substrate with a gate oxide therebetween; source and drain extension regions formed in a surface of the relaxed SiGe substrate and containing an N type impurity; and low vacancy regions, containing an interstitial element or a vacancy-trapping element, formed in the source and drain extension regions, wherein an implant profile of the interstitial element or the vacancy-trapping element fully contains an N type impurity profile, whereby diffusion retardation is maximized. 8. The semiconductor device of claim 7, wherein the interstitial element is Si or O and the vacancy-trapping element is F, N, Xe, Ar, He, Kr or a noble gas element. 9. The semiconductor device of claim 7, wherein each of the interstitial element or the vacancy-trapping element is ion-implanted. 10. The semiconductor device of claim 7, wherein the semiconductor device is an N type device. 11. The semiconductor device of claim 7, wherein the N type impurity is ion-implanted in a self-aligned manner. 12. The semiconductor device of claim 7, wherein the vacancy-trapping element forms vacancy-based clusters. 13. A semiconductor device comprising: a relaxed SiGe-based substrate; a gate electrode formed on the SiGe-based substrate with a gate oxide therebetween; source and drain extension regions formed in an upper surface of the SiGe substrate and containing an N type impurity; and low vacancy regions, containing an interstitial element or a vacancy-trapping element, that substantially overlap the source and drain extension regions, wherein an implant profile of the interstitial element or the vacancy-trapping element fully contains an N type impurity profile, whereby diffusion retardation is maximized. 14. The semiconductor device of claim 13, wherein the interstitial element is Si or O and the vacancy-trapping element is F, N, Xe, Ar, He, Kr or a noble gas element. 15. The semiconductor device of claim 13, wherein each of the interstitial element or the vacancy-trapping element is ion-implanted. 16. The semiconductor device of claim 13, wherein the semiconductor device is an N type device. 17. The semiconductor device of claim 13, wherein the N type impurity is ion-implanted in a self-aligned manner and the vacancy-trapping element forms vacancy-based clusters.