초록

Programmable memory built-in self-test (MBIST) methods, apparatus, and systems are disclosed. Exemplary embodiments of the disclosed technology can be used, for example, to test one or more memories located on an integrated circuit during manufacturing testing.

대표청구항 ▼

We claim: 1. A method for testing at least one memory included in an integrated circuit using a test algorithm comprising one or more test steps described by algorithm instructions and configuration instructions, the method comprising: receiving the configuration and algorithm instructions delivere

We claim: 1. A method for testing at least one memory included in an integrated circuit using a test algorithm comprising one or more test steps described by algorithm instructions and configuration instructions, the method comprising: receiving the configuration and algorithm instructions delivered to an instruction memory of a memory testing portion of the integrated circuit; evaluating the received configuration instructions; determining that all algorithm instructions for one of the test steps have been received; evaluating the algorithm instructions for said one of the test steps following the determination that all of the algorithm instructions for said one of the test steps have been received, wherein the evaluating the algorithm instructions comprises addressing at least selected cells within the memory to which test data is to be applied to test the cells according to the at least one test algorithm, the act of addressing the selected cells being accomplished so as to address cells at the functional operating speed of the memory at least during certain memory access operations within the one of the one or more test steps; applying test data to the addressed cells; and analyzing output results read from the at least selected cells to which test data is applied to determine whether the test results match expected test results from the selected cells in response to the applied test data. 2. The method according to claim 1 wherein the act of addressing comprises addressing cells in at least one inner loop of one of the test algorithms nested within at least one outer loop of the one of the test algorithms, and wherein the act of addressing comprises addressing transitions between cells of the inner and outer loop so as to implement at least one testing algorithm comprising a nested loop algorithm. 3. The method according to claim 2 wherein the act of addressing comprises addressing cells in a plurality of nested loops and wherein the act of addressing comprises addressing transitions between cells of the different loops so as to implement at least one testing algorithm comprising a plurality of nested loops. 4. The method according to claim 3 wherein the act of addressing comprises addressing cells at the functional operating speed of the memory at least during memory access operations within a loop. 5. The method according to claim 4 comprising the act of recording diagnostic data for selected errors that become revealed by functional operating speed testing. 6. The method according to claim 1 comprising the act of delivering configuration instructions and algorithm instructions to the integrated circuit to implement a plurality of testing algorithms. 7. The method according to claim 1 wherein the act of decoding comprises decoding algorithm instructions in parallel with the decoding of configuration instructions. 8. The method according to claim 7 further comprising the act of executing memory operations for a first test step described by a first set of algorithm instructions stored in at least one first buffer while at least one second buffer is receiving a second set of algorithm instructions describing memory operations for a second test step and executing operations of the second test step stored in the second buffer while the first buffer is receiving a third set of algorithm instructions describing memory operations for a third test step, wherein the second test step is subsequent to the first test step and the third test step is subsequent to the second test step. 9. The method according to claim 8 wherein the at least one first buffer comprises at least one first base loop buffer for storing sequences of operations performed on all base addresses in accordance with a testing step and wherein the at least one second buffer comprises at least one second base loop buffer for storing sequences of operations performed on all base addresses in accordance with a testing algorithm step, wherein the at least one first buffer also comprises a first local loop buffer for storing sequences of operations performed on local addresses that differ from a base address associated with an operation of the first base loop buffer, and wherein the at least one second buffer also comprises a second local loop buffer for storing sequences of operations performed on local addresses that differ from a base address associated with an operation of the second base loop buffer. 10. The method according to claim 9 wherein the local addresses comprise all addresses of the memory cells other than the base address for an operation associated with the base address. 11. The method according to claim 9 wherein the local address comprises a subset of less than all of the addresses of the memory cells other than the base address for an operation associated with the base address. 12. The method according to claim 9 comprising the act of reaching the next base address in the base loop buffers from the current base address in the base loop buffer following the execution of the sequence of operations stored in the local address buffer associated with the current base address. 13. The method according to claim 9 wherein the act of addressing comprises addressing commencing with a first cell of a selected group of cells to the last cell of the selected group of cells. 14. The method according to claim 9 wherein the act of addressing comprises addressing all cells of the memory starting from a reference cell. 15. The method according to claim 14 wherein the reference cell is at the first row and first column address of an array of cells of the memory. 16. The method of claim 1, wherein at least one of the configuration instructions is evaluated over multiple clock cycles. 17. The method of claim 1, wherein the said one of the test steps is a first one of the test steps, the method further comprising repeating the method of claim 1 for a second one of the test steps. 18. A method for testing at least one memory included in an integrated circuit comprising: decoding configuration and algorithm instructions delivered to an instruction memory of a memory testing portion of the integrated circuit; determining at least one test algorithm comprising test steps to be applied to the memory from the decoded instructions; addressing at least selected cells within the memory to which test data is to be applied to test the cells according to the at least one test algorithm, the act of addressing the selected cells being accomplished so as to address cells at the functional operating speed of the memory at least during certain memory access operations within a test step; applying test data to the addressed cells; analyzing output results read from the at least selected cells to which test data is applied to determine whether the test results match expected test results from the selected cells in response to the applied test data; executing memory operations for a first test step stored in at least one first buffer while at least one second buffer is receiving memory operations for a second test step and executing operations of the second test step stored in the second buffer while the first buffer is receiving memory operations for a third test step, wherein the second test step is subsequent to the first test step and the third test step is subsequent to the second test step, wherein the act of decoding comprises decoding algorithm instructions in parallel with the decoding of configuration instructions, wherein the at least one first buffer comprises at least one first base loop buffer for storing sequences of operations performed on all base addresses in accordance with a testing step, wherein the at least one second buffer comprises at least one second base loop buffer for storing sequences of operations performed on all base addresses in accordance with a testing algorithm step, wherein the at least one first buffer also comprises a first local loop buffer for storing sequences of operations performed on local addresses that differ from a base address associated with an operation of the first base loop buffer, wherein the at least one second buffer also comprises a second local loop buffer for storing sequences of operations performed on local addresses that differ from a base address associated with an operation of the second base loop buffer, and wherein the act of addressing at least selected cells in the memory comprises determining row and column addresses for each of the selected cells in parallel. 19. A method of providing an MBIST circuit, comprising: receiving a user designation of a plurality of nested loops required to apply one or more memory testing algorithms desired by the user to be run by the MBIST circuit to test one or more memories of an integrated circuit; and synthesizing the MBIST circuit, wherein the MBIST circuit is configured to have the capability of running, according to a plurality of instructions comprising algorithm instructions and configuration instructions, the one or more memory testing algorithms having the plurality of nested loops designated by the user, wherein the MBIST circuit comprises an address generator configured to generate respective addresses for each nested loop in the plurality of nested loops, the respective addresses comprising row values and column values, and wherein the MBIST circuit further comprises a first decoder configured to identify one of the plurality of instructions as an algorithm instruction or a configuration instruction. 20. The method of claim 19, further comprising a second decoder configured to decode algorithm instructions and a third decoder configured to decode configuration instructions. 21. A method of providing an MBIST circuit comprising: receiving a user designation of at least one category of memory testing algorithms from a plurality of categories of algorithms; and synthesizing the MBIST circuit, wherein the MBIST circuit is configured to have the capability of running the memory testing algorithms of the at least one category of algorithms designated by the user, and wherein the MBIST circuit comprises first and second buffers configured to store algorithm instructions of the memory testing algorithms, each of the first and second buffers comprising a base loop buffer and a local loop buffer. 22. The method according to claim 21 wherein the user designated at least one category of algorithms comprising at least one algorithm that includes a plurality of nested loops. 23. A method of providing an MBIST controller comprising: receiving a user designation of a plurality of address generators required for an MBIST circuit to run memory testing algorithms desired to be run by a user; and synthesizing the MBIST circuit, wherein the MBIST circuit is configured to have the plurality of address generators designated by the user for running the memory testing algorithms desired to be run by the user, and wherein at least some of the address generators are configured to determine, in parallel, row and column addresses for each of selected memory cells within a memory being tested by the MBIST circuit.