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Body biasing structure of SOI 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-027/01
출원번호 US-0423696 (2006-06-12)
등록번호 US-7432552 (2008-10-07)
우선권정보 KR-10-2005-0050107(2005-06-11)
발명자 / 주소
  • Park,Byung Gook
  • Kim,Tae Hoon
  • Park,II Han
출원인 / 주소
  • Seoul National University Industry Foundation
  • Samsung Electronics Co., Ltd.
대리인 / 주소
    Marger Johnson & McCollom PC
인용정보 피인용 횟수 : 30  인용 특허 : 5

초록

A body biasing structure of devices connected in series on an SOI substrate is provided. According to some embodiments, the shallow junction of common source/drain regions enables all devices to bias by only one body contact on an SOI substrate like a conventional bulk MOSFET, and the floating body

대표청구항

What is claimed is: 1. A body biasing structure for Silicon-On-Insulator (SOI) devices comprising: an SOI substrate; an active region in the SOI substrate comprising: a body biasing contact region; a common active region connected to the body biasing contact region; and a device active region conne

이 특허에 인용된 특허 (5)

  1. Machesney Brian J. (Burlington VT) Mandelman Jack A. (Stormville NY) Nowak Edward J. (Essex VT), Contacted body silicon-on-insulator field effect transistor.
  2. Burr James B., Partially depleted SOI device having a dedicated single body bias means.
  3. Dachtera, William R.; Joshi, Rajiv V.; Rausch, Werner A., Silicon on insulator field effect transistors having shared body contact.
  4. Jang, Tae-Ho, Silicon-on-insulator (SOI) substrate and method for manufacturing the same.
  5. Shigenobu Maeda JP; Shigeto Maegawa JP, TFT with partially depleted body.

이 특허를 인용한 특허 (30)

  1. Willard, Simon Edward; Ranta, Tero Tapio, AC coupling modules for bias ladders.
  2. Dribinsky, Alexander; Kim, Tae Youn; Kelly, Dylan J.; Brindle, Christopher N., Circuit and method for controlling charge injection in radio frequency switches.
  3. Shapiro, Eric S.; Allison, Matt, Circuit and method for improving ESD tolerance and switching speed.
  4. Ranta, Tero Tapio; Bawell, Shawn; Greene, Robert W.; Brindle, Christopher N.; Englekirk, Robert Mark, Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals.
  5. Ranta, Tero Tapio; Bawell, Shawn; Greene, Robert W.; Brindle, Christopher N.; Englekirk, Robert Mark, Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals.
  6. Ranta, Tero Tapio; Bawell, Shawn; Greene, Robert W.; Brindle, Christopher N.; Englekirk, Robert Mark, Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals.
  7. Bawell, Shawn; Broughton, Robert; Bacon, Peter; Greene, Robert W.; Ranta, Tero Tapio, Digitally tuned capacitors with tapered and reconfigurable quality factors.
  8. Nobbe, Dan William; Olson, Chris; Kovac, David, Hot carrier injection compensation.
  9. Chandrasekhar, Uday; Helm, Mark, Memory kink checking.
  10. Chandrasekhar, Uday; Helm, Mark A., Memory kink checking.
  11. Chandrasekhar, Uday; Helm, Mark A., Memory kink checking.
  12. Chandrasekhar, Uday; Helm, Mark A., Memory kink checking.
  13. Ranta, Tero Tapio, Method and apparatus for use in digitally tuning a capacitor in an integrated circuit device.
  14. Brindle, Christopher N.; Stuber, Michael A.; Kelly, Dylan J.; Kemerling, Clint L.; Imthurn, George P.; Welstand, Robert B.; Burgener, Mark L., Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink.
  15. Brindle, Christopher N.; Stuber, Michael A.; Kelly, Dylan J.; Kemerling, Clint L.; Imthurn, George; Welstand, Robert B.; Burgener, Mark L., Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink.
  16. Brindle, Christopher N.; Deng, Jie; Genc, Alper; Yang, Chieh-Kai, Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction.
  17. Brindle, Christopher N.; Deng, Jie; Genc, Alper; Yang, Chieh-Kai, Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction.
  18. Stuber, Michael A.; Brindle, Christopher N.; Kelly, Dylan J.; Kemerling, Clint L.; Imthurn, George P.; Burgener, Mark L.; Dribinsky, Alexander; Kim, Tae Youn, Method and apparatus improving gate oxide reliability by controlling accumulated charge.
  19. Stuber, Michael A.; Brindle, Christopher N.; Kelly, Dylan J.; Kemerling, Clint L.; Imthurn, George P.; Welstand, Robert B.; Burgener, Mark L.; Dribinsky, Alexander; Kim, Tae Youn, Method and apparatus improving gate oxide reliability by controlling accumulated charge.
  20. Moschiano, Violante; Roohparvar, Frankie; Santin, Giovanni; Sarin, Vishal; Vahidimowlavi, Allahyar; Vali, Tommaso, Method for kink compensation in a memory.
  21. Moschiano, Violante; Roohparvar, Frankie; Santin, Giovanni; Sarin, Vishal; Vahidimowlavi, Allahyar; Vali, Tommaso, Method for kink compensation in a memory.
  22. Moschiano, Violante; Roohparvar, Frankie; Santin, Giovanni; Sarin, Vishal; Vahidimowlavi, Allahyar; Vali, Tommaso, Method for kink compensation in a memory.
  23. Reedy, Ronald Eugene; Nobbe, Dan William; Ranta, Tero Tapio; Liss, Cheryl V.; Kovac, David, Methods and apparatuses for use in tuning reactance in a circuit device.
  24. Ranta, Tero Tapio, Positive logic digitally tunable capacitor.
  25. Facchini, Marc; Bacon, Peter, Power splitter with programmable output phase shift.
  26. Olson, Chris, Semiconductor devices with switchable ground-body connection.
  27. Burgener, Mark L.; Cable, James S., Switch circuit and method of switching radio frequency signals.
  28. Burgener, Mark L.; Cable, James S., Switch circuit and method of switching radio frequency signals.
  29. Englekirk, Robert Mark, Tuning capacitance to enhance FET stack voltage withstand.
  30. Englekirk, Robert Mark, Tuning capacitance to enhance FET stack voltage withstand.
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