초록 ▼

A charge pump circuit is disclosed, including: a dummy current path comprising a first junction node; a normal current path comprising a second junction node; a switch, coupled between the dummy current path and the normal current path; wherein when the switch is closed a first voltage is at the fir

A charge pump circuit is disclosed, including: a dummy current path comprising a first junction node; a normal current path comprising a second junction node; a switch, coupled between the dummy current path and the normal current path; wherein when the switch is closed a first voltage is at the first junction node and the second junction node, and when the switch is open a second voltage is at the first junction node; and a comparator, for comparing the first voltage and the second voltage to balance a current mismatch of the charge pump circuit. The disclosed charge pump circuit can be implemented in a phase locked loop system.

대표청구항 ▼

What is claimed is: 1. A charge pump circuit, comprising: a first current providing circuit, for providing a current source to the charge pump circuit; a second current providing circuit, for providing a current sink to the charge pump circuit; a dummy current path, coupled between the first curren

What is claimed is: 1. A charge pump circuit, comprising: a first current providing circuit, for providing a current source to the charge pump circuit; a second current providing circuit, for providing a current sink to the charge pump circuit; a dummy current path, coupled between the first current providing circuit and the second current providing circuit, comprising a first switch element, a second switch element, and a first junction node between the first switch element and the second switch element; a first capacitor, coupled to the first junction node; a normal current path, coupled between the first current providing circuit and the second current providing circuit, comprising a third switch element, a fourth switch element, and a second junction node between the third switch element and the fourth switch element; a second capacitor, coupled to the second junction node; a voltage follower, coupled to the second junction node of the normal current path; a switch, coupled between an output node of the voltage follower and the first junction node of the dummy current path; wherein when the switch is switched on in a first period, a first voltage is at the first junction node and the second junction node, and when the switch is switched off in a second period, the first voltage is at the second junction node and a second voltage is at the first junction node; and a calibration circuit, coupled to the first junction node of the dummy current path and the output node of the voltage follower, for comparing the first voltage and the second voltage to balance a current mismatch between the current source and the current sink, the calibration circuit comprising: a comparator, coupled to the first junction node and the second junction node, for comparing the first voltage and the second voltage to generate a corresponding logic level; and a state machine, coupled to the comparator, for inputting a calibrating current to the first current providing circuit and the second current providing circuit according to the logic level. 2. The charge pump circuit of claim 1, wherein the switch is a CMOS transistor. 3. The charge pump circuit of claim 1, wherein if the logic level is a high logic level, the state machine will input a low current level to the second current providing circuit, and if the logic level is a low logic level, the state machine will input a high current level to the first current providing circuit. 4. The charge pump circuit of claim 1, wherein the amount of the calibrating current is dependent on the charge pump circuit. 5. The charge pump circuit of claim 1, wherein the voltage follower is an amplifier. 6. A method for calibrating a current mismatch in a charge pump circuit, wherein the charge pump comprises a first current providing circuit, a second current providing circuit, a dummy current path coupled between the first current providing circuit and the second current providing circuit, and a normal current path coupled between the first current providing circuit and the second current providing circuit, the dummy current path comprises a first junction node, and the normal path comprises a second junction node, the method comprising: providing a voltage follower coupled to the second junction node; providing a switch coupled between the first junction node and the voltage follower; inputting a current source to the first current providing circuit; inputting a current sink to the second current providing circuit; switching on the switch in a first time period to obtain a first voltage at the first junction node and the second junction node; switching off the switch in a second time period to obtain a second voltage at the first junction node; and comparing the first voltage and the second voltage to balance a current mismatch between the current source and the current sink, comprising: comparing the first voltage and the second voltage to generate a corresponding logic level; and inputting a calibrating current to the first current providing circuit and the second current providing circuit according to the logic level. 7. The method of claim 6, wherein the step of providing a switch coupled between the first junction node and the voltage follower comprises: providing a CMOS transistor coupled between the first junction node and the voltage follower. 8. The method of claim 6, wherein the step of inputting a calibrating current to the first current providing circuit and the second current providing circuit according to the logic level comprises: if the logic level is a high logic level, inputting a low current level to the second current providing circuit, and if the logic level is a low logic level, inputting a high current level to the first current providing circuit. 9. The method of claim 6, wherein the amount of the calibrating current is dependent on the charge pump circuit. 10. The method of claim 6, wherein the step of providing a voltage follower coupled to the second junction node comprises: providing an amplifier coupled to the second junction node. 11. A phase locked loop system, comprising: a phase comparator for receiving a reference clock signal and a clock signal, and for comparing a phase of the reference clock signal with a phase of the clock signal so as to output a phase difference signal; a charge-pump circuit capable of calibrating a current mismatch for producing an output current which depends on the phase difference signal; a loop filter for converting the output current of the charge-pump circuit into an output voltage; and a voltage controlled oscillator for generating a signal having a frequency which depends on the output voltage of the loop filter as a clock signal; wherein the charge pump circuit comprises: a first current providing circuit, for providing a current source to the charge pump circuit; a second current providing circuit, for providing a current sink to the charge pump circuit; a dummy current path, coupled between the first current providing circuit and the second current providing circuit, comprising a first switch element, a second switch element, and a first junction node between the first switch element and the second switch element; a first capacitor, coupled to the first junction node; a normal current path, coupled between the first current providing circuit and the second current providing circuit, comprising a third switch element, a fourth switch element, and a second junction node between the third switch element and the fourth switch element; a second capacitor, coupled to the second junction node; a voltage follower, coupled to the second junction node of the normal current path; a switch, coupled between an output node of the voltage follower and the first junction node of the dummy current path; wherein when the switch is switched on in a first period, a first voltage is at the first junction node and the second junction node, and when the switch is switched off in a second period, the first voltage is at the second junction node and a second voltage is at the first junction node; and a calibration circuit, coupled to the first junction node of the dummy current path and the output node of the voltage follower, for comparing the first voltage and the second voltage to balance a current mismatch between the current source and the current sink, the calibration circuit comprising: a comparator, coupled to the first junction node and the second junction node, for comparing the first voltage and the second voltage to generate a corresponding logic level; and a state machine, coupled to the comparator, for inputting a calibrating current to the first current providing circuit and the second current providing circuit according to the logic level. 12. The phase locked loop system of claim 11, wherein the switch is a CMOS transistor. 13. The phase locked loop system of claim 11, wherein if the logic level is a high logic level, the state machine will input a low current level to the second current providing circuit, and if the logic level is a low logic level, the state machine will input a high current level to the first current providing circuit. 14. The phase locked loop system of claim 11, wherein the amount of the calibrating current is dependent on the charge pump circuit. 15. The phase locked loop system of claim 11, wherein the voltage follower is an amplifier.