초록 ▼

The present invention relates to a VPP voltage generator that generates a stable VPP voltage. The VPP voltage generator of the present invention generates a stable VPP voltage. Therefore, power consumption can be saved, a precharge time of word line can be prevented from increasing and a tRCD charac

The present invention relates to a VPP voltage generator that generates a stable VPP voltage. The VPP voltage generator of the present invention generates a stable VPP voltage. Therefore, power consumption can be saved, a precharge time of word line can be prevented from increasing and a tRCD characteristic can be improved. It is thus possible to improve the operational performance of semiconductor memory devices.

대표청구항 ▼

What is claimed is: 1. A VPP voltage generator comprising: an oscillator circuit that periodically generates a pumping control signal of a pulse form based on an oscillation cycle according to first and second cycle control signals, the oscillator circuit being enabled in response to an enable cont

What is claimed is: 1. A VPP voltage generator comprising: an oscillator circuit that periodically generates a pumping control signal of a pulse form based on an oscillation cycle according to first and second cycle control signals, the oscillator circuit being enabled in response to an enable control signal; a pumping circuit that performs a charge pumping operation in response to the pumping control signal, thus generating a VPP voltage; a VPP voltage detector that detects the level of the VPP voltage and outputs first and second detection signals according to the detection result; a cycle control circuit that outputs the first and second cycle control signals to the oscillator circuit and is configured to control the oscillation cycle in response to the first and second detection signals, wherein the cycle control circuit includes: a first control logic circuit that outputs the first cycle control signal and an inverted first cycle control signal in response to the first detection signal; and a second control logic circuit that outputs the second cycle control signal and an inverted second cycle control signal in response to the second detection signal; and an enable control circuit that compares the VPP voltage with a reference voltage and generates the enable control signal according to the comparison result, in response to a word line activation signal. 2. The VPP voltage generator of claim 1, wherein the enable control circuit enables the enable control signal if the VPP voltage is lower than the reference voltage when the word line activation signal is enabled, and the oscillator circuit is enabled when the enable control signal is enabled. 3. The VPP voltage generator of claim 1, wherein the VPP voltage detector includes: a voltage divider circuit that divides the VPP voltage according to a predetermined resistance ratio and outputs the divided voltage; a differential amplifier that compares the divided voltage with a reference voltage and outputs a compare signal according to the comparison result; and an output logic circuit that outputs the first and second detection signals in response to the compare signal. 4. The VPP voltage generator of claim 3, wherein the voltage divider circuit includes at least one fuse, and the resistance ratio of the voltage divider circuit is changed according to a cutting or non-cutting state of the fuse. 5. The VPP voltage generator of claim 3, wherein the differential amplifier outputs the compare signal as a high level when the divided voltage is lower than the reference voltage, and the output logic circuit enables the first detection signal and disables the second detection signal when the compare signal is a high level. 6. The VPP voltage generator of claim 1, wherein the first control logic circuit enables the first cycle control signal during a predetermined time when the first detection signal is enabled, and disables the first cycle control signal when the first detection signal is disabled, and the second control logic circuit enables the second cycle control signal during a predetermined time when the second detection signal is enabled, and disables the first cycle control signal when the second detection signal is disabled. 7. The VPP voltage generator of claim 1, wherein the oscillator circuit includes: a pulse generator that outputs an internal logic signal and the pumping control signal in response to the enable control signal and a delay circuit; and a delay circuit whose delay time is controlled according to the first and second cycle control signals and the inverted first and second cycle control signals, wherein the delay circuit delays the internal logic signal for the delay time and outputs a delay circuit. 8. The VPP voltage generator of claim 7, wherein the pulse generator includes: a first inverter that inverts the enable signal and outputs an inverted enable signal; a NOR gate that outputs the internal logic signal in response to the inverted enable signal and the delay signal; a second inverter that inverts the internal logic signal; and a third inverter that inverts the output signal of the second inverter and outputs the inverted signal as the pumping control signal. 9. The VPP voltage generator of claim 7, wherein when the first cycle control signal is disabled and the second cycle control signal is enabled, the delay time of the delay circuit is increased, and when the first cycle control signal is enabled and the second cycle control signal is disabled, the delay time of the delay circuit is reduced, when the delay time is increased, the cycle of the pumping control signal is increased, and when the delay time is reduced, the cycle of the pumping control signal is reduced and when the cycle of the pumping control signal is reduced, the pumping circuit raises the VPP voltage. 10. The VPP voltage generator of claim 8, wherein the delay circuit includes a plurality of delay control circuits that are connected in series between an output terminal of the NOR gate and one of input terminals of the NOR gate, and each of the plurality of delay control circuits includes: a fourth inverter that inverts an input signal received through an input node and outputs an inverted signal; a first unit delay circuit connected to the input node parallel to the fourth inverter, for delaying the input signal during a first unit time; a second unit delay circuit connected to the input node parallel to the fourth inverter, for delaying or not delaying the input signal for a second unit time in response to the first cycle control signal and the inverted first cycle control signal; and a third unit delay circuit connected to the input node parallel to the fourth inverter, for delaying or not delaying the input signal for a third unit time in response to the second cycle control signal and the inverted second cycle control signal. 11. The VPP voltage generator of claim 10, wherein the first unit delay circuit includes first capacitors connected to the input node in parallel, the second unit delay circuit includes: second capacitors; and first switching circuits, which are connected between the input node and the second capacitors, respectively, and are turned on or off in response to the first cycle control signal and the inverted first cycle control signal, and the third unit delay circuit includes: third capacitors; and second switching circuits, which are connected between the input node and the third capacitors, respectively, and are turned on or off in response to the second cycle control signal and the inverted second cycle control signal. 12. A VPP voltage generator comprising: an oscillator circuit that periodically generates a pumping control signal of a pulse form based on an oscillation cycle set according to first and second detection signals, the oscillator circuit being enabled in response to an enable control signal; a pumping circuit that performs a charge pumping operation in response to the pumping control signal, thus generating a VPP voltage; a VPP voltage detector that detects the level of the VPP voltage and outputs to the oscillator circuit the first and second detection signals to control the oscillation cycle according to the detection result, wherein the VPP voltage detector includes: a voltage divider circuit that divides the VPP voltage according to a predetermined resistance ratio and outputs the divided voltage; a differential amplifier that compares the divided voltage with a reference voltage and outputs a compare signal according to the comparison result; and an output logic circuit that outputs the first and second detection signals and inverted first and second detection signals in response to the compare signal; and an enable control circuit that compares the VPP voltage with a reference voltage and generates the enable control signal according to the comparison result, in response to a word line activation signal. 13. The VPP voltage generator of claim 12, wherein the enable control circuit enables the enable control signal if the VPP voltage is lower than the reference voltage when the word line activation signal is enabled, and the oscillator circuit is enabled when the enable control signal is enabled. 14. The VPP voltage generator of claim 12, wherein the voltage divider circuit includes at least one fuse, and the resistance ratio of the voltage divider circuit is changed according to a cutting or non-cutting state of the fuse. 15. The VPP voltage generator of claim 12, wherein the differential amplifier outputs the compare signal as a high level when the divided voltage is lower than the reference voltage, and the output logic circuit enables the first detection signal and disables the second detection signal when the compare signal is a high level. 16. The VPP voltage generator of claim 12, wherein the oscillator circuit includes: a pulse generator that outputs an internal logic signal and the pumping control signal in response to the enable control signal and a delay circuit; and a delay circuit whose delay time is controlled according to the first and second detection signals and the inverted first and second detection signals, wherein the delay circuit delays the internal logic signal for the delay time and outputs a delay circuit. 17. The VPP voltage generator of claim 16, wherein the pulse generator includes: a first inverter that inverts the enable signal and outputs an inverted enable signal; a NOR gate that outputs the internal logic signal in response to the inverted enable signal and the delay signal; a second inverter that inverts the internal logic signal; and a third inverter that inverts the output signal of the second inverter and outputs the inverted signal as the pumping control signal. 18. The VPP voltage generator of claim 16, wherein when the first detection signal is disabled and the second detection signal is enabled, the delay time of the delay circuit is increased, and when the first detection signal is enabled and the second detection signal is disabled, the delay time of the delay circuit is reduced, when the delay time is increased, the cycle of the pumping control signal is increased, and when the delay time is reduced, the cycle of the pumping control signal is reduced and when the cycle of the pumping control signal is reduced, the pumping circuit raises the VPP voltage. 19. The VPP voltage generator of claim 17, wherein the delay circuit includes a plurality of delay control circuits that are connected in series between an output terminal of the NOR gate and one of input terminals of the NOR gate, and each of the plurality of delay control circuits includes: a fourth inverter that inverts an input signal received through an input node and outputs an inverted signal; a first unit delay circuit connected to the input node parallel to the fourth inverter, for delaying the input signal during a first unit time; a second unit delay circuit connected to the input node parallel to the fourth inverter, for delaying or not delaying the input signal for a second unit time in response to the first cycle control signal and the inverted first cycle control signal; and a third unit delay circuit connected to the input node parallel to the fourth inverter, for delaying or not delaying the input signal for a third unit time in response to the second cycle control signal and the inverted second cycle control signal. 20. The VPP voltage generator of claim 19, wherein the first unit delay circuit includes first capacitors connected to the input node in parallel, the second unit delay circuit includes: second capacitors; and first switching circuits, which are connected between the input node and the second capacitors, respectively, and are turned on or off in response to the first cycle control signal and the inverted first cycle control signal, and the third unit delay circuit includes: third capacitors; and second switching circuits, which are connected between the input node and the third capacitors, respectively, and are turned on or off in response to the second cycle control signal and the inverted second cycle control signal.