초록 ▼

A PRAM and programming method are disclosed. The PRAM includes a memory cell array including a test cell, a write driver applying a program pulse and providing a program current to the memory cell array, a sense amplification and verification circuit reading data programmed in the memory cell array

A PRAM and programming method are disclosed. The PRAM includes a memory cell array including a test cell, a write driver applying a program pulse and providing a program current to the memory cell array, a sense amplification and verification circuit reading data programmed in the memory cell array and performing a program verify operation on the data, and a program loop control unit storing program verification result for the test cell at each program loop during test operation and generating the program pulse according to the program verification result to control the start of the program loop during normal operation.

대표청구항 ▼

What is claimed is: 1. A phase change random access memory (PRAM) performing a program loop operation, the PRAM comprising: a memory cell array including a test cell; a write driver applying a program pulse and providing a program current to the memory cell array; a sense amplification and verifica

What is claimed is: 1. A phase change random access memory (PRAM) performing a program loop operation, the PRAM comprising: a memory cell array including a test cell; a write driver applying a program pulse and providing a program current to the memory cell array; a sense amplification and verification circuit reading data programmed in the memory cell array and performing a program verify operation on the data; and a program loop control unit storing program verification result for the test cell at each program loop during test operation and generating the program pulse according to the program verification result to control the start of the program loop during normal operation. 2. The PRAM of claim 1, wherein the program loop control unit comprises: a program loop circuit providing the program pulse to the write driver according to the program verification result of the sense amplification and verification circuit; a loop storage circuit storing the program verification result for each of the program loops during the test operation; and a program loop controller controlling the start of the program loop according to the program verification result stored in the loop storage circuit during normal operation. 3. The PRAM of claim 2, wherein the program loop controller controls the finish of the program loop according to the program verification result stored in the loop storage circuit. 4. The PRAM of claim 2, further comprising a switch outputting the program verification result to a pad, wherein the program verification result is stored in the loop storage circuit. 5. The PRAM of claim 2, wherein the loop storage circuit comprises: a loop storage register temporarily storing the program verification result for each of the program loops; and a loop setting unit storing the program verification result stored in the register. 6. The PRAM of claim 5, wherein the loop setting unit includes a nonvolatile memory cell storing the program verification result. 7. The PRAM of claim 6, wherein the nonvolatile memory cell comprises; a memory element implemented with a phase change material; and, a select element selecting the nonvolatile memory cell. 8. The PRAM of claim 5, wherein the loop setting unit comprises a fuse box storing the program verification result. 9. The PRAM of claim 8, further comprises a switch outputting the program verification result to a pad, wherein the program verification result is stored in the loop storage circuit, and a fuse in the fuse box is cut in relation to the program verification result read via the pad. 10. The PRAM of claim 2, wherein the loop storage circuit stores the program verification result for each of the program loops derived during chip level testing following manufacture. 11. The PRAM of claim 1, wherein the test operation or normal operation is controlled by data stored in a mode register set (MRS). 12. The PRAM of claim 1, wherein the write driver increases the program current incrementally in relation to successive program loops. 13. The PRAM of claim 1, wherein the memory cell array comprises a plurality of memory cells, each of the memory cells including a memory element implemented with a phase change material and a select element selecting the memory element, wherein the select element is a diode or a transistor. 14. A method of programming a phase change random access memory (PRAM), wherein memory cells within the PRAM are programmed by a program loop operation including a plurality of program loops, and the PRAM includes a memory cell array, a write driver providing a program current to the memory cell array according to a program loop, and a sense amplification and verification circuit reading data programmed in the memory cell array and performing a program verify operation in each program loop, the method comprising: performing a test operation to store program verification results for each program loop; and performing a normal operation that controls the start of the program loop according to the program verification result. 15. The method of claim 14, wherein the performing of the normal operation controls the finish of the program loop according to the program verification result. 16. The method of claim 14, wherein the program verification results are temporarily stored in a register and then stored in a nonvolatile memory cell. 17. The method of claim 14, wherein the program verification results are temporarily stored in a register and then stored in a fuse box. 18. The method of claim 14, wherein the storing of the program verification result is performed during chip level testing following manufacture of the PRAM. 19. The method of claim 14, wherein the test operation or the normal operation are indicated by data stored in a mode register set (MRS). 20. The method of claim 14, wherein the write driver increases the program current incrementally according to the program loop.