초록 ▼

A driver circuit for a PRAM (phase-change random access memory) device includes a write driver that generates a set/reset current in response to a set/reset pulse. In addition, a temperature compensator controls a pulse width of the set/reset pulse in response to a peripheral temperature of the PRAM

A driver circuit for a PRAM (phase-change random access memory) device includes a write driver that generates a set/reset current in response to a set/reset pulse. In addition, a temperature compensator controls a pulse width of the set/reset pulse in response to a peripheral temperature of the PRAM device. For example, the temperature compensator maintains the pulse width to be substantially constant irrespective of the peripheral temperature. In another example, the temperature compensator decreases the pulse width for higher peripheral temperature.

대표청구항 ▼

What is claimed is: 1. A PRAM (phase-change random access memory) comprising: a write driver that generates a set current or a reset current in response to a set pulse or a reset pulse; a temperature compensator that controls a pulse width of the set pulse or the reset pulse in response to a temper

What is claimed is: 1. A PRAM (phase-change random access memory) comprising: a write driver that generates a set current or a reset current in response to a set pulse or a reset pulse; a temperature compensator that controls a pulse width of the set pulse or the reset pulse in response to a temperature of the PRAM; and a temperature detector that generates a control signal indicating the temperature of the PRAM, wherein the temperature compensator includes at least one forward or delay controller having a respective current controlled by said control signal with said respective current setting an end of the set pulse or the reset pulse for determining said pulse width. 2. The PRAM of claim 1, wherein a voltage level of the control signal increases with increase of the temperature. 3. The PRAM of claim 1, wherein the temperature compensator maintains the pulse width to be substantially constant irrespective of the temperature. 4. The PRAM of claim 3, wherein the temperature compensator includes: a receiver for generating a first signal in response to a data pulse signal and a write activation signal; a pulse controller that generates a second signal that is a delayed form of the first signal with a delay that depends on said respective current of said forward or delay controller; and a pulse generator that generates the set pulse or the reset pulse from the first and second signals. 5. The PRAM of claim 4, wherein the pulse controller includes said at least one forward or delay controller with: at least one forward controller that each advances the end of the set pulse or the reset pulse for a higher level of the temperature; and at least one delay controller that each delays the end of the set pulse or the reset pulse for a higher level of the temperature. 6. The PRAM of claim 1, wherein the temperature compensator decreases the pulse width for a higher level of the temperature. 7. The PRAM of claim 6, wherein the temperature compensator includes: a receiver for generating a first signal in response to a data pulse signal and a write activation signal; a pulse controller that generates a second signal that is a delayed form of the first signal with a delay that depends on said respective current of said forward or delay controller; and a pulse generator that generates the set pulse or the reset pulse from the first and second signals. 8. The PRAM of claim 7 wherein the pulse controller includes said at least one forward or delay controller with: at least one forward controller that each advances the end of the set pulse or the reset pulse for a higher level of the temperature. 9. A PRAM (phase-change random access memory) comprising: a write driver that generates a set current or a reset current in response to a set pulse or a reset pulse; means for controlling a pulse width of the set pulse or the reset pulse in response to a temperature of the PRAM; and means for generating a control signal indicating the temperature of the PRAM; wherein the means for controlling the pulse width includes at least one forward or delay controller having a respective current controlled by said control signal with said respective current setting an end of the set pulse or the reset pulse for determining said pulse width. 10. The PRAM of claim 9, wherein the means for controlling includes: means for maintaining the pulse width to be substantially constant irrespective of the temperature. 11. The PRAM of claim 10, wherein the means for maintaining includes: means for advancing the end of the set pulse or the reset pulse for a higher level of the temperature; and means for delaying the end of the set pulse or the reset pulse for a higher level of the temperature, wherein said end of the set pulse or the reset pulse depends on said respective current through said at least one forward or delay controller. 12. The PRAM of claim 9, wherein the means for controlling includes: means for decreasing the pulse width for a higher level of the temperature. 13. The PRAM of claim 12, wherein the means for decreasing includes: means for advancing the end of the set pulse or the reset pulse for a higher level of the temperature, wherein said end of the set pulse or the reset pulse depends on said respective current through said at least one forward or delay controller. 14. A method for programming a PRAM (phase-change random access memory), comprising: generating a set current or a reset current in response to a set pulse or a reset pulse; and controlling a pulse width of the set pulse or the reset pulse in response to a temperature of the PRAM; and generating a control signal indicating the temperature of the PRAM, wherein the step of controlling the pulse width includes controlling a respective current through at least one forward or delay controller using said control signal with said respective current setting an end of the set pulse or the reset pulse for determining said pulse width. 15. The method of claim 14, further comprising: increasing a voltage level of the control signal with increase of the temperature. 16. The method of claim 14, further comprising: maintaining the pulse width to be substantially constant irrespective of the temperature. 17. The method of claim 16, further comprising: advancing the end of the set pulse or the reset pulse for a higher level of the temperature; and delaying the end of the set pulse or the reset pulse for a higher level of the temperature, wherein said end of the set pulse or the reset pulse depends on said respective current through said at least one forward or delay controller. 18. The method of claim 14, further comprising: decreasing the pulse width for a higher level of the temperature. 19. The method of claim 18, further comprising: advancing the end of the set pulse or the reset pulse for a higher level of the temperature, wherein said end of the set pulse or the reset pulse depends on said respective current through said at least one forward or delay controller.