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A duty detector may include a first amplifier and/or an integrator. The first amplifier may be configured to receive a first signal and a complementary first signal, differential-amplify the first signal and the complementary first signal, and/or output the differential-amplified first signal to an

A duty detector may include a first amplifier and/or an integrator. The first amplifier may be configured to receive a first signal and a complementary first signal, differential-amplify the first signal and the complementary first signal, and/or output the differential-amplified first signal to an output terminal and the differential-amplified complementary first signal to a complementary output terminal. The integrator may be connected to the output terminal and the complementary output terminal of the first amplifier, configured to integrate the differential-amplified first signal and the differential-amplified complementary first signal, and/or configured to output a duty detection signal.

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What is claimed is: 1. A duty detector, comprising: a first amplifier configured to receive a first signal and a complementary first signal, differential-amplify the first signal and the complementary first signal, and output the differential-amplified first signal to an output terminal and the dif

What is claimed is: 1. A duty detector, comprising: a first amplifier configured to receive a first signal and a complementary first signal, differential-amplify the first signal and the complementary first signal, and output the differential-amplified first signal to an output terminal and the differential-amplified complementary first signal to a complementary output terminal; and an integrator connected to the output terminal and the complementary output terminal of the first amplifier, configured to integrate the differential-amplified first signal and the differential-amplified complementary first signal, and configured to output a duty detection signal, wherein the integrator includes, a second amplifier configured to receive the differential-amplified first signal through a positive input terminal, receive the differential-amplified complementary first signal through a negative input terminal, differential-amplify the received signals, and output the duty detection signal, a third amplifier configured to receive the differential-amplified complementary first signal through a positive input terminal, receive the differential-amplified first signal through a negative input terminal, differential-amplify the received signals, and output a complementary duty detection signal, a first capacitor coupled between the negative input terminal of the second amplifier and an output terminal of the second amplifier, a second capacitor coupled between the negative input terminal of the third amplifier and an output terminal of the third amplifier, a third capacitor coupled to the output terminal of the second amplifier, and a fourth capacitor coupled to the output terminal of the third amplifier. 2. The duty detector of claim 1, wherein the integrator comprises: a first reset transistor connected in parallel with the first capacitor; and a second reset transistor connected in parallel with the second capacitor. 3. The duty detector of claim 1, wherein the third and fourth capacitors have capacitances larger than capacitances of the first and second capacitors. 4. The duty detector of claim 1, wherein the first amplifier comprises: a first load transistor coupled between a power supply voltage source and the output terminal of the first amplifier; a second load transistor coupled between the power supply voltage source and the complementary output terminal of the first amplifier; a first input transistor coupled between the output terminal of the first amplifier and a common node, the first input transistor including a gate configured to receive the complementary first signal; a second input transistor coupled between the complementary output terminal of the first amplifier and the common node, the second input transistor including a gate configured to receive the first signal; and a bias transistor coupled between the common node and a ground voltage source, the bias transistor including a gate configured to receive a bias signal. 5. The duty detector of claim 4, wherein the first amplifier comprises: a comparator configured to compare one of the differential-amplified first signal and the differential-amplified complementary first signal to a reference voltage, wherein an output signal of the comparator is applied to the gates of the first and second load transistors. 6. A duty detector comprising: a first amplifier configured to receive a first signal and a complementary first signal, differential-amplify the first signal and the complementary first signal, and output the differential-amplified first signal to an output terminal and the differential-amplified complementary first signal to a complementary output terminal: an integrator connected to the output terminal and the complementary output terminal of the first amplifier, configured to integrate the differential-amplified first signal and the differential-amplified complementary first signal, and configured to output a duty detection signal; and a comparator configured to compare one of the differential-amplified first signal and the differential-amplified complementary first signal to a reference voltage and control a load of the first amplifier in response to the comparison result. 7. The duty detector of claim 6, wherein the integrator comprises: a second amplifier configured to receive the differential-amplified first signal through a positive input terminal, receive the differential-amplified complementary first signal through a negative input terminal, differential-amplify the received signals, and output the duty detection signal; a third amplifier configured to receive the differential-amplified complementary first signal through a positive input terminal, receive the differential-amplified first signal through a negative input terminal, differential-amplify the received signals, and output a complementary duty detection signal; a first capacitor coupled between the negative input terminal of the second amplifier and an output terminal of the second amplifier; a second capacitor coupled between the negative input terminal of the third amplifier and an output terminal of the third amplifier; a third capacitor coupled to the output terminal of the second amplifier; and a fourth capacitor coupled to the output terminal of the third amplifier. 8. The duty detector of claim 7, wherein the integrator comprises: a first reset transistor connected in parallel with the first capacitor; and a second reset transistor connected in parallel with the second capacitor. 9. The duty detector of claim 7, wherein the third and fourth capacitors have capacitances larger than capacitances of the first and second capacitors. 10. The duty detector of claim 6, wherein the first amplifier comprises: a first load transistor coupled between a power supply voltage source and the output terminal of the first amplifier, the first load transistor including a gate configured to receive the comparison result of the comparator; a second load transistor coupled between the power supply voltage source and the complementary output terminal of the first amplifier, the second load transistor including a gate configured to receive the comparison result of the comparator; a first input transistor coupled between the output terminal of the first amplifier and a common node, the first input transistor including a gate configured to receive the complementary first signal; a second input transistor coupled between the complementary output terminal of the first amplifier and the common node, the second input transistor including a gate configured to receive the first signal; and a bias transistor coupled between the common node and a ground voltage source, the bias transistor including a gate configured to receive a bias signal. 11. A duty detection/correction circuit comprising: a duty corrector configured to correct a duty cycle of an input clock signal in response to a duty detection signal and output a first signal and a complementary first signal; and a duty detector configured to detect the duty cycle of the first signal and output the duty detection signal, the duty detector including, a first amplifier configured to receive the first signal and the complementary first signal, differential-amplify the first signal and the complementary first signal, and output the differential-amplified first signal to an output terminal and the differential-amplified complementary first signal to a complementary output terminal, and an integrator connected to the output terminal and the complementary output terminal of the first amplifier, configured to integrate the differential-amplified first signal and the differential-amplified complementary first signal, and configured to output the duty detection signal. 12. The duty detection/correction circuit of claim 11, wherein the integrator comprises: a second amplifier configured to receive the differential-amplified first signal through a positive input terminal, receive the differential-amplified complementary first signal through a negative input terminal, differential-amplify the received signals, and output the duty detection signal; a third amplifier configured to receive the differential-amplified complementary first signal through a positive input terminal, receive the differential-amplified first signal through a negative input terminal, differential-amplify the received signals, and output a complementary duty detection signal; a first capacitor coupled between the negative input terminal of the second amplifier and an output terminal of the second amplifier; a second capacitor coupled between the negative input terminal of the third amplifier and an output terminal of the third amplifier; a third capacitor coupled to the output terminal of the second amplifier; and a fourth capacitor coupled to the output terminal of the third amplifier. 13. The duty detection/correction circuit of claim 12, wherein the integrator comprises: a first reset transistor connected in parallel with the first capacitor; and a second reset transistor connected in parallel with the second capacitor. 14. The duty detection/correction circuit of claim 12, wherein the third and fourth capacitors have capacitances larger than capacitances of the first and second capacitors. 15. The duty detection/correction circuit of claim 11, wherein the first amplifier comprises: a first load transistor coupled between a power supply voltage source and the output terminal of the first amplifier; a second load transistor coupled between the power supply voltage source and the complementary output terminal of the first amplifier; a first input transistor coupled between the output terminal of the first amplifier and a common node, the first input transistor including a gate configured to receive the complementary first signal; a second input transistor coupled between the complementary output terminal of the first amplifier and the common node, the second input transistor including a gate configured to receive the first signal; and a bias transistor coupled between the common node and a ground voltage source, the bias transistor including a gate configured to receive a bias signal. 16. The duty detection/correction circuit of claim 15, wherein the first amplifier comprises: a comparator configured to compare one of the differential-amplified first signal and the differential-amplified complementary signal to a reference voltage, wherein an output signal of the comparator is applied to the gates of the first and second load transistors. 17. The duty detection/correction circuit of claim 11, wherein the duty corrector includes an amplifier. 18. The duty detection/correction circuit of claim 11, wherein the duty detector includes a differential charge pump. 19. A duty detection/correction circuit comprising: a duty corrector configured to correct a duty cycle of an input clock signal in response to a duty detection signal and output a first signal and a complementary first signal; and a duty detector configured to detect the duty cycle of the first signal and output the duty detection signal, wherein the duty detector includes, a first amplifier configured to receive the first signal and the complementary first signal, differential-amplify the first signal and the complementary first signal, and output the differential-amplified first signal to an output terminal and the differential-amplified complementary first signal to a complementary output terminal, an integrator connected to the output terminal and the complementary output terminal of the first amplifier, configured to integrate the differential-amplified first signal and the differential-amplified complementary first signal, and configured to output the duty detection signal, and a comparator configured to compare one of the differential-amplified first signal and the differential-amplified complementary first signal to a reference voltage and control a load of the first amplifier in response to the comparison result. 20. The duty detection/correction circuit of claim 19, wherein the integrator comprises: a second amplifier configured to receive the differential-amplified first signal through a positive input terminal, receive the differential-amplified complementary first signal through a negative input terminal, differential-amplify the received signals, and output the duty detection signal; a third amplifier configured to receive the differential-amplified complementary first signal through a positive input terminal, receive the differential-amplified first signal through a negative input terminal, differential-amplify the received signals, and output a complementary duty detection signal; a first capacitor coupled between the negative input terminal of the second amplifier and an output terminal of the second amplifier; a second capacitor coupled between the negative input terminal of the third amplifier and an output terminal of the third amplifier; a third capacitor coupled to the output terminal of the second amplifier; and a fourth capacitor coupled to the output terminal of the third amplifier. 21. The duty detection/correction circuit of claim 20, wherein the integrator comprises: a first reset transistor connected in parallel with the first capacitor; and a second reset transistor connected in parallel with the second capacitor. 22. The duty detection/correction circuit of claim 20, wherein the third and fourth capacitors have capacitances larger than capacitances of the first and second capacitors. 23. The duty detection/correction circuit of claim 19, wherein the first amplifier comprises: a first load transistor coupled between a power supply voltage source and the output terminal of the first amplifier, the first load transistor including a gate configured to receive the comparison result of the comparator; a second load transistor coupled between the power supply voltage source and the complementary output terminal of the first amplifier, the second load transistor including a gate configured to receive the comparison result of the comparator; a first input transistor coupled between the output terminal of the first amplifier and a common node, the first input transistor including a gate configured to receive the complementary first signal; a second input transistor coupled between the complementary output terminal of the first amplifier and the common node, the second input transistor including a gate configured to receive the first signal; and a bias transistor coupled between the common node and a ground voltage source, the bias transistor including a gate configured to receive a bias signal. 24. The duty detection/correction circuit of claim 19, wherein the duty corrector includes an amplifier. 25. The duty detection/correction circuit of claim 19, wherein the duty detector includes a differential charge pump.