초록 ▼

A Phased Locked Loop (PLL) circuit includes: a clock signal generating unit for generating a first clock signal and a second clock signal of which the phase differs from the first clock signal by Π/2; a computing unit for computing first phase comparison results showing the results of comparin

A Phased Locked Loop (PLL) circuit includes: a clock signal generating unit for generating a first clock signal and a second clock signal of which the phase differs from the first clock signal by Π/2; a computing unit for computing first phase comparison results showing the results of comparing the phases of a signal wherein the first clock signal is subjected to phase shifting with the PSK modulation signal and second phase comparison results showing the results of comparing the phases of a signal wherein the second clock signal is subjected to phase shifting with the PSK modulation signal based on first and second parameters, the first clock signal, the second clock signal, and the PSK modulation signal; a control direction setting unit for virtually controlling the control angle; a parameter control unit; and a reading control unit for controlling the timing of reading data from the PSK modulation.

대표청구항 ▼

What is claimed is: 1. A Phase Locked Loop (PLL) circuit comprising: a clock signal generating means configured to generate a first clock signal with a frequency approximately equal to that of a Phase Shift Keying (PSK) modulation signal which is a digital signal subjected to PSK modulation, and a

What is claimed is: 1. A Phase Locked Loop (PLL) circuit comprising: a clock signal generating means configured to generate a first clock signal with a frequency approximately equal to that of a Phase Shift Keying (PSK) modulation signal which is a digital signal subjected to PSK modulation, and a second clock signal of which the phase differs from said first clock signal by Π/2; a computing means configured to compute, for each time period of a predetermined length, first phase comparison results showing the results of comparing the phases of a signal wherein said first clock signal is subjected to phase shifting of an amount equivalent to a control angle which is an angle to virtually control the phases of said first clock signal and said second clock signal with said PSK modulation signal during said time period, and second phase comparison results showing the results of comparing the phases of a signal wherein said second clock signal is subjected to phase shifting of an amount equivalent to said control angle with said PSK modulation signal during said time period, based on a first parameter corresponding to the cosine of said control angle, a second parameter corresponding to the sine of said control angle, said first clock signal, said second clock signal, and said PSK modulation signal; a control direction setting means configured to set the control direction for virtually controlling said control angle based on said first phase comparison results and said second phase comparison results; a parameter control means configured to control said first parameter and said second parameter based on said control angle virtually controlled in said control direction; and a reading control means configured to control the timing of reading data from said PSK modulation signal based on said control angle virtually controlled in said control direction. 2. The PLL circuit according to claim 1, wherein said computing means compute said first phase comparison results and said second phase comparison results for each cycle of said PSK modulation signal. 3. The PLL circuit according to claim 1, wherein said computing means compute said first phase comparison results and said second phase comparison results for every ½ cycle of said PSK modulation signal, and wherein said control direction setting means finds said control direction for every ½ cycle of said PSK modulation signal, and determines said control direction for every cycle of said PSK modulation signal based on the two control directions obtained. 4. The PLL circuit according to claim 1, wherein said computing means compute a value wherein the sum of a first multiplied value having multiplied said first parameter, said PSK modulation signal, and said first clock signal, and a second multiplied value having multiplied said second parameter, said PSK modulation signal, and said second clock signal, is cumulatively added over said time period as said first phase comparison results, and compute a value wherein the sum of a third multiplied value having inverted the sign of the value wherein said second parameter, said PSK modulation signal, and said first clock signal are multiplied, and a fourth multiplied value having multiplied said first parameter, said PSK modulation signal, and said second clock signal, is cumulatively added over said time period as said second phase comparison results. 5. The PLL circuit according to claim 4, said computing means further comprising: a multiplying means configured to compute said first through said fourth multiplied values; a first cumulative adding means configured to cumulatively add said first multiplied value every other time, over said time period; a second cumulative adding means configured to cumulatively add said first multiplied value every other time, so as to alternate with said first adding means, over said time period; a third cumulative adding means configured to cumulatively add said second multiplied value every other time, over said time period; a fourth cumulative adding means configured to cumulatively add said second multiplied value every other time, so as to alternate with said third adding means, over said time period; a fifth cumulative adding means configured to cumulatively add said third multiplied value every other time, over said time period; a sixth cumulative adding means configured to cumulatively add said third multiplied value every other time, so as to alternate with said fifth adding means, over said time period; a seventh cumulative adding means configured to cumulatively add said fourth multiplied value every other time, over said time period; a eighth cumulative adding means configured to cumulatively add said fourth multiplied value every other time, so as to alternate with said seventh adding means, over said time period; a first adding means configured to compute the sum of said first cumulatively added value computed with said first cumulative adding means and said second cumulatively added value computed with said third cumulative adding means or the sum of said first cumulatively added value computed with said second cumulative adding means and said second cumulatively added value computed with said fourth cumulative adding means; and a second adding means configured to compute the sum of said third cumulatively added value computed with said fifth cumulative adding means and said fourth cumulatively added value computed with said seventh cumulative adding means or the sum of said third cumulatively added value computed with said sixth cumulative adding means and said fourth cumulatively added value computed with said eighth cumulative adding means. 6. The PLL circuit according to claim 1, wherein said reading control means control the timing for reading data from said PSK modulation signal so as to read data twice at a timing wherein the phase differs by Π for a cycle of said PSK modulation signal. 7. A phase control method comprising the steps of: generating a first clock signal with a frequency approximately equal to that of a Phase Shift Keying (PSK) modulation signal serving as a digital signal subjected to PSK modulation, and a second clock signal of which the phase differs from said first clock signal by Π/2; computing, for each time period of a predetermined length, first phase comparison results showing the results of comparing the phases of a signal wherein said first clock signal is subjected to phase shifting of an amount equivalent to a control angle which is an angle to virtually control the phases of said first clock signal and said second clock signal with said PSK modulation signal during said time period, and second phase comparison results showing the results of comparing the phases of a signal wherein said second clock signal is subjected to phase shifting of an amount equivalent to said control angle with said PSK modulation signal during said time period based on a first parameter corresponding to the cosine of said control angle, a second parameter corresponding to the sine of said control angle, said first clock signal, said second clock signal, and said PSK modulation signal; setting the control direction for virtually controlling said control angle based on said first phase comparison results and said second phase comparison results; controlling said first parameter and said second parameter based on said control angle virtually controlled in said control direction; and controlling the timing of reading data from said PSK modulation signal based on said control angle virtually controlled in said control direction. 8. An Integrated Circuit (IC) chip with the functionality to demodulate a Phase Shift Keying (PSK) modulation signal serving as a digital signal subjected to PSK modulation, having a Phase Locked Loop (PLL) circuit, comprising: a clock signal generating means configured to generate a first clock signal with a frequency approximately equal that of said PSK modulation signal and a second clock signal of which the phase differs from said first clock signal by Π/2; a computing means configured to compute, for each time period of a predetermined length, first phase comparison results showing the results of comparing the phases of a signal wherein said first clock signal is subjected to phase shifting of an amount equivalent to a control angle which is an angle to virtually control the phases of said first clock signal and said second clock signal with said PSK modulation signal during said time period and second phase comparison results showing the results of comparing the phases of a signal wherein said second clock signal is subjected to phase shifting of an amount equivalent to said control angle with said PSK modulation signal during said time period, based on a first parameter corresponding to the cosine of said control angle, a second parameter corresponding to the sine of said control angle, said first clock signal, said second clock signal, and said PSK modulation signal; a control direction setting means configured to set the control direction for virtually controlling said control angle based on said first phase comparison results and said second phase comparison results; a parameter control means configured to control said first parameter and said second parameter based on said control angle virtually controlled in said control direction; and a reading control means configured to control the timing of reading data from said PSK modulation signal based on said control angle virtually controlled in said control direction. 9. The IC chip according to claim 8, having non-contact IC card functionality, read/write functionality, or read functionality. 10. A Phase Locked Loop (PLL) circuit comprising: a clock signal generating unit configured to generate a first clock signal with a frequency approximately equal that of a Phase Shift Keying (PSK) modulation signal serving as a digital signal subjected to PSK modulation and a second clock signal of which the phase differs from said first clock signal by Π/2; a computing unit configured to compute, for each time period of a predetermined length, first phase comparison results showing the results of comparing the phases of a signal wherein said first clock signal is subjected to phase shifting of an amount equivalent to a control angle which is an angle to virtually control the phases of said first clock signal and said second clock signal with said PSK modulation signal during said time period and second phase comparison results showing the results of comparing the phases of a signal wherein said second clock signal is subjected to phase shifting of an amount equivalent to said control angle with said PSK modulation signal during said time period, based on a first parameter corresponding to the cosine of said control angle, a second parameter corresponding to the sine of said control angle, said first clock signal, said second clock signal, and said PSK modulation signal; a control direction setting unit configured to set the control direction for virtually controlling said control angle based on said first phase comparison results and said second phase comparison results; a parameter control unit configured to control said first parameter and said second parameter based on said control angle virtually controlled in said control direction; and a reading control unit configured to control the timing of reading data from said PSK modulation signal based on said control angle virtually controlled in said control direction. 11. An Integrated Circuit (IC) chip with the functionality to demodulate a Phase Shift Keying (PSK) modulation signal serving as a digital signal subjected to PSK modulation, having a Phase Locked Loop (PLL) circuit, comprising: a clock signal generating unit configured to generate a first clock signal with a frequency as with that of said PSK modulation signal and a second clock signal of which the phase differs from said first clock signal by Π/2; a computing unit configured to compute, for each time period of a predetermined length, first phase comparison results showing the results of comparing the phases of a signal wherein said first clock signal is subjected to phase shifting of an amount equivalent to a control angle which is an angle to virtually control the phases of said first clock signal and said second clock signal with said PSK modulation signal during said time period and second phase comparison results showing the results of comparing the phases of a signal wherein said second clock signal is subjected to phase shifting of an amount equivalent to said control angle with said PSK modulation signal during said time period, based on a first parameter corresponding to the cosine of said control angle, a second parameter corresponding to the sine of said control angle, said first clock signal, said second clock signal, and said PSK modulation signal; a control direction setting unit configured to set the control direction for virtually controlling said control angle based on said first phase comparison results and said second phase comparison results; a parameter control unit configured to control said first parameter and said second parameter based on said control angle virtually controlled in said control direction; and a reading control unit configured to control the timing of reading data from said PSK modulation signal based on said control angle virtually controlled in said control direction.