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Bi-processor architecture for secure systems 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H04L-009/32
출원번호 US-0558367 (2006-11-09)
등록번호 US7984301 (2011-07-06)
발명자 / 주소
  • Kaabouch, Majid
  • Le Cocquen, Eric
출원인 / 주소
  • Inside Contactless S.A.
대리인 / 주소
    Fish & Richardson P.C.
인용정보 피인용 횟수 : 23  인용 특허 : 21

초록 ▼

Systems, methods and program products for a first central processing unit (CPU) configured to perform tasks that do not require manipulation of sensitive information and a second CPU that is configured to perform tasks that manipulate the sensitive information on behalf of the first CPU. The first C

대표청구항 ▼

What is claimed is: 1. A system comprising:a first central processing unit (CPU) configured to perform tasks that do not require manipulation of sensitive information;a second CPU configured to perform tasks that manipulate the sensitive information on behalf of the first CPU;a secure communication

이 특허에 인용된 특허 (21)

  1. Wasson,Stephen L.; Varn,David K.; Ralston,John D., Apparatus and method for a programmable security processor.
    상세보기
  2. Jaffe, Joshua M.; Kocher, Paul C.; Jun, Benjamin C., Balanced cryptographic computational method and apparatus for leak minimizational in smartcards and other cryptosystems.
    상세보기
  3. Kocher Paul C. ; Jaffe Joshua M. ; Jun Benjamin C., Des and other cryptographic, processes with leak minimization for smartcards and other cryptosystems.
    상세보기
  4. McKelvey Mark Ambrose, Embedded security processor.
    상세보기
  5. Callum Gordon GB, Enhanced security semiconductor device, semiconductor circuit arrangement and method or production thereof.
    상세보기
  6. Jaffe, Joshua M.; Kocher, Paul C.; Jun, Benjamin C., Hardware-level mitigation and DPA countermeasures for cryptographic devices.
    상세보기
  7. Sunahara Hazime (Kawasaki JPX), Inter-processor transmission system having data link which automatically and periodically reads and writes the transfer.
    상세보기
  8. Kocher, Paul C., Leak-resistant cryptographic indexed key update.
    상세보기
  9. Kocher Paul C. ; Jaffe Joshua M., Leak-resistant cryptographic method and apparatus.
    상세보기
  10. Paul C. Kocher ; Joshua M. Jaffe, Leak-resistant cryptographic method and apparatus.
    상세보기
  11. Gupta,Reema; Wang,Yao; Tringale,Alesia, Messaging mechanism employing mailboxes for inter processor communications.
    상세보기
  12. Carloganu Marius M.,FRX ; Sheets John F., Method and apparatus for operating resources under control of a security module or other secure processor.
    상세보기
  13. Messerges Thomas S. ; Dabbish Ezzat A. ; Puhl Larry, Method and apparatus for preventing information leakage attacks on a microelectronic assembly.
    상세보기
  14. Curry Duncan ; Yu Arthur Y. ; Mok Tsung D., Microcontroller including a single memory module having a data memory sector and a code memory sector and supporting simultaneous read/write access to both sectors.
    상세보기
  15. Best,Robert M., Secure distribution of portable game software.
    상세보기
  16. Benhammou Jean-Pierre ; Colnot Cedric V.,FRX, Secure memory having anti-wire tapping.
    상세보기
  17. Benhammou Jean-Pierre ; Baran Dennis F. ; Tonge Phillip D. ; Terry ; Jr. Edward L., Secure memory having multiple security levels.
    상세보기
  18. Kocher Paul C. ; Jaffe Joshua M., Secure modular exponentiation with leak minimization for smartcards and other cryptosystems.
    상세보기
  19. Candelore Brant ; Sprunk Eric, Secure processor with external memory using block chaining and block re-ordering.
    상세보기
  20. Mason Martin T. ; Kunnari Nancy D. ; Kuo Harry H., Secure programmable logic device.
    상세보기
  21. Kocher Paul C. ; Jaffe Joshua M. ; Jun Benjamin C., Using unpredictable information to minimize leakage from smartcards and other cryptosystems.
    상세보기

이 특허를 인용한 특허 (23)

  1. Ellis, Frampton E., Computer or microchip controlled by a firewall-protected master controlling microprocessor and firmware.
    상세보기
  2. Ellis, Frampton E., Computer or microchip including a network portion with RAM memory erasable by a firewall-protected master controller.
    상세보기
  3. Ellis, Frampton E., Computer or microchip with a master controller connected by a secure control bus to networked microprocessors or cores.
    상세보기
  4. Ellis, Frampton E., Computer or microchip with a master controller connected by a secure control bus to networked microprocessors or cores.
    상세보기
  5. Ellis, Frampton E., Computer or microchip with a master controller connected by a secure control bus to networked microprocessors or cores.
    상세보기
  6. Ellis, Frampton E., Computer or microchip with a secure control bus connecting a central controller to volatile RAM and the volatile RAM to a network-connected microprocessor.
    상세보기
  7. Ellis, Frampton E., Computer or microchip with a secure system BIOS and a secure control bus connecting a central controller to many network-connected microprocessors and volatile RAM.
    상세보기
  8. Ellis, Frampton E., Computer or microchip with a secure system bios having a separate private network connection to a separate private network.
    상세보기
  9. Ellis, Frampton E., Computer or microchip with an internal hardware firewall and a master controlling device.
    상세보기
  10. Ellis, Frampton E., Computer or microchip with its system bios protected by one or more internal hardware firewalls.
    상세보기
  11. Ellis, Frampton E., Computers and microchips with a faraday cage, with a side protected by an internal hardware firewall and unprotected side connected to the internet for network operations, and with internal hardware compartments.
    상세보기
  12. Ellis, III, Frampton E., Computers and microchips with a portion protected by an internal hardware firewalls.
    상세보기
  13. Ellis, III, Frampton E., Computers and microchips with a side protected by an internal hardware firewall and an unprotected side connected to a network.
    상세보기
  14. Ellis, III, Frampton E., Computers or microchips with a hardware side protected by a primary internal hardware firewall leaving an unprotected hardware side connected to a network, and with multiple internal hardware compartments protected by multiple secondary interior hardware firewalls.
    상세보기
  15. Ellis, Frampton E., Computers or microchips with a primary internal hardware firewall and with multiple internal harware compartments protected by multiple secondary interior hardware firewalls.
    상세보기
  16. Ellis, Frampton E., Method of securely controlling through one or more separate private networks an internet-connected computer having one or more hardware-based inner firewalls or access barriers.
    상세보기
  17. Ellis, Frampton E., Method of using one or more secure private networks to actively configure the hardware of a computer or microchip.
    상세보기
  18. Ellis, Frampton E., Methods of securely controlling through one or more separate private networks an internet-connected computer having one or more hardware-based inner firewalls or access barriers.
    상세보기
  19. Ellis, Frampton E., Microchip with faraday cages and internal flexibility sipes.
    상세보기
  20. Ellis, Frampton E, Microchips with an internal hardware firewall.
    상세보기
  21. Ellis, III, Frampton E., Microchips with an internal hardware firewall protected portion and a network portion with microprocessors which execute shared processing operations with the network.
    상세보기
  22. Ellis, III, Frampton E., Microchips with an internal hardware firewall that by its location leaves unprotected microprocessors or processing units which performs processing with a network.
    상세보기
  23. Ellis, Frampton E., Personal computer, smartphone, tablet, or server with a buffer zone without circuitry forming a boundary separating zones with circuitry.
    상세보기

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